Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

Abstract: According to an apparatus form of the invention, integrated circuitry on a single chip includes a bit-programmable voltage regulator supplying voltage to first circuitry on the chip. The integrated circuitry also includes second circuitry operable for characterizing performance of the first circuitry. Control circuitry on the chip is operable, responsive to the characterizing performed by the second circuitry, to output at least one digital control bit for controlling the regulator output voltage supplying the first circuitry. In another aspect, the integrated circuitry is operable to receive an externally generated, time-based reference signal, and the second circuitry includes an on-chip oscillator for generating a performance characterizing signal. The performance characterizing signal varies in frequency in correspondence with the performance of the first circuitry.

Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

Abstract: According to an apparatus form of the invention, oscillator circuitry for operating a number of inverters in a loop (also known as a “ring”) includes a number of inverters. The inverters include a series of M inverters and a series of N inverters. The M inverters have signal propagation delay of m and the N inverters have signal propagation delay of n. The circuitry also includes means for selecting whether to exclude the N inverters from operating in the loop operable for receiving a select signal on a data input. The selecting means times assertion of the select signal on an output to select the number of inverters. In order to glitchlessly change the number of inverters operating in the loop, the selecting means has a certain delay greater than delay n.

Abstract: According to an apparatus form of the invention, oscillator circuitry for operating a number of inverters in a loop (also known as a “ring”) includes a number of inverters. The inverters include a series of M inverters and a series of N inverters. The M inverters have signal propagation delay of m and the N inverters have signal propagation delay of n. The circuitry also includes means for selecting whether to exclude the N inverters from operating in the loop operable for receiving a select signal on a data input. The selecting means times assertion of the select signal on an output to select the number of inverters. In order to glitchlessly change the number of inverters operating in the loop, the selecting means has a certain delay greater than delay n.

Abstract: In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.

Abstract: In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.

Abstract: First current is conducted through a first path to adjust a voltage at a node toward a predetermined level in response to the voltage being within a first subrange of voltages. Second current is conducted through a second path to adjust the voltage at the node toward the predetermined level in response to the voltage being within a second subrange of voltages.