Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: A programmable delay line is introduced that produces a delayed signal that is glitch free and without metastability conditions. The programmable delay line includes a synchronizer circuit and a programmable delay circuit. The synchronizer circuit is configured to receive an input signal and one or more control signals. The synchronizer circuit synchronizes the one or more control signals to the input signal, producing one or more synchronized control signals. The programmable delay circuit is configured to utilizing the synchronized control signals to add an amount of delay to the input signal, producing a delayed version of the input signal that is glitch free and without metastability conditions. The control signals control the amount of delay added to the input signal based on, for example, process, voltage and temperature (PVT) variations.

Abstract: In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal and an IO device output node. Additionally, the IO device includes a plurality of drivers coupled between the IO device input and output nodes, each having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together. A drain of each driver's second n-channel FET and each driver's first p-channel FET is coupled to the IO device output node, while a gate of each driver's first n-channel FET is coupled to the IO device input node.