Abstract: Offset correction in a differential successive approximation register (SAR) analog-to-digital converter (ADC) is accomplished with a capacitor-reduced digital-to-analog converter (DAC) topology to enable offset correction without the need for a dedicated compensation DAC. This eliminates addition analog circuitry and die area. To perform the offset correction, the differential SAR ADC couples together inputs thereof to create an offset voltage, converts the offset voltage into a digital representation thereof, stores the digital representation of the offset voltage in an offset register, and corrects for the offset voltage by generating an offset compensation voltage with the capacitor-reduced array DAC controlled by the digital representation stored in the offset register. The digital representation controls scaling of reference voltages to the reduced capacitor array DAC associated with a least-significant-bit (LSB) of the differential SAR ADC.

Abstract: A differential successive approximation register (SAR) analog-to-digital converter (ADC) with wide input common-mode range adds one step to its conversion process. No additional circuitry is required for full rail-to-rail common mode voltage operation. In a first step the top-plate nodes vcp and vcn may be reset to a fixed voltage vcm. Then in a next step sampling may be performed while leaving vcp and vcn floating but shorted. Whereby a single node vx is formed, which provides for simple capacitive voltage division. Thereafter a standard sequential SAR bit-by-bit analog-to-digital conversion is performed. the voltage at node vx will follow vcmin during the entire sampling phase, with a limitation in rate of change only limited by the RC time constant of the shorting switch and the sampling capacitors. This will have much higher bandwidth than any active OTA-based tracking circuit.

Abstract: Offset correction in a differential successive approximation register (SAR) analog-to-digital converter (ADC) is accomplished with a capacitor-reduced digital-to-analog converter (DAC) topology to enable offset correction without the need for a dedicated compensation DAC. This eliminates addition analog circuitry and die area. To perform the offset correction, the differential SAR ADC couples together inputs thereof to create an offset voltage, converts the offset voltage into a digital representation thereof, stores the digital representation of the offset voltage in an offset register, and corrects for the offset voltage by generating an offset compensation voltage with the capacitor-reduced array DAC controlled by the digital representation stored in the offset register. The digital representation controls scaling of reference voltages to the reduced capacitor array DAC associated with a least-significant-bit (LSB) of the differential SAR ADC.

Abstract: A differential successive approximation register (SAR) analog-to-digital converter (ADC) with wide input common-mode range adds one step to its conversion process. No additional circuitry is required for full rail-to-rail common mode voltage operation. In a first step the top-plate nodes vcp and vcn may be reset to a fixed voltage vcm. Then in a next step sampling may be performed while leaving vcp and vcn floating but shorted. Whereby a single node vx is formed, which provides for simple capacitive voltage division. Thereafter a standard sequential SAR bit-by-bit analog-to-digital conversion is performed. the voltage at node vx will follow vcmin during the entire sampling phase, with a limitation in rate of change only limited by the RC time constant of the shorting switch and the sampling capacitors. This will have much higher bandwidth than any active OTA-based tracking circuit.