Abstract: A peripheral device in a processor system which can generate system level wait states to temporarily stop the clock of a processor is disclosed. The system comprises at least one peripheral device, a wait-unknowledgeable processor, and a clock controller. The peripheral device generates a wait signal when the peripheral device is not ready to service a request, and the clock controller selectively turns off the clock signal to the processor. In this way, the processor can be waited by the peripheral for an arbitrary number of clock cycles until the processor request is serviced by the peripheral, even though the processor does not provide a dedicated wait input signal.

Abstract: The invention disclosed herein is directed to a scatter/gather direct memory access (DMA) controller that is able to perform DMA data transfers from/to noncontiguous areas in a memory to/from contiguous areas in a memory. The DMA controller has a control register comprised of three fields, a line segment offset, a line size and a line count, respectively, to efficiently control an imaging data transfer using a fixed-offset manner. The line segment offset field sets a fixed offset value to the next line segment in a memory, the line size field sets the size of the line segment, and the line segment count field counts the number of line segments remaining in a DMA transfer.

Abstract: The present application describes systems and methods for performing direct memory access (DMA) from a source memory to a destination memory. One such method comprises retrieving address values to specify starting locations in the source memory and the destination memory; retrieving a size value to specify a number of units of a data line; retrieving a count value to specify a number of data lines to be transferred from the source memory to a destination memory, in which the data line consists a plurality of consecutive data units; retrieving an offset value to specify a fixed separation spacing between data lines being transferred consecutively; transferring the data lines per line each time from the source memory to the destination memory consecutively according to the source address value, the destination address value, the size value, the count value and the offset value; and terminating the transferring in response to the transferring of all data lines of the DMA transfer.

Abstract: A direct memory access (DMA) controller supporting multiple outstanding software requests in the same channel (intra-channel) is disclosed. The DMA controller comprises a plurality of channel configuration registers, a channel request arbiter, a tail search unit, a channel prediction unit, a command/request entry generator and a request queue. The channel configuration registers output a set of actual channel parameters, the channel prediction unit generates a set of predicted channel parameters, and the command/request entry generator sends a request to the request queue based on the output of the tail search unit. The command/request entry generator uses actual channel parameters to generate control commands and requests if valid outstanding intra-channel requests are not found during the tail search of the presently outstanding requests in the DMA controller; otherwise, the command/request entry generator uses predicted channel parameters from the most recently scheduled intra-channel software request.

Abstract: A standby self-detection mechanism in a DMA controller which reduces the power consumption by dynamically controlling the on/off states of at least one clock tree driven by global clock-gating circuitry is disclosed. The DMA controller comprises a standby self-detection unit, a scheduler, at least one set of channel configuration registers associated with at least one DMA channel, and an internal request queue which holds already scheduled DMA requests that are presently outstanding in the DMA controller. The standby self-detection unit drives a signal to a global clock-gating circuitry to selectively turn on or off at least one of the clock trees to the DMA controller, depending on whether the DMA controller is presently performing a DMA transfer.

Abstract: In a DSP system, a processor accesses a plurality of accelerators arranged in a multi-tier architecture, wherein a primary accelerator is coupled between the processor and a plurality of secondary accelerators. The processor accesses at least one of the secondary accelerators by sending an instruction with ID field for the primary accelerator only. The primary accelerator selects one of the secondary accelerators according to an address stored in an address pointer register. The number of the accessible secondary accelerators depends on the address addressable by the address pointer register. The processor can also update or modify the address in the address pointer register by an immediate value or an offset address in the instruction.

Abstract: A memory arbiter in a processor system which can generate system level wait state to temporarily stop the clock to a processor is disclosed. The processor system comprises a memory, a processor, a memory arbiter and a clock controller. The memory arbiter generates a wait signal when the memory is not ready to service a memory request, and the clock controller selectively turns off a clock signal to the processor. In this way, the processor that cannot be waited by means of a dedicated wait input signal can be included in the arbitration scheme to improve the performance of the processor system.

Abstract: A DSP system includes a DSP processor, at least one accelerator and an accelerator interface connected between the DSP processor and the at least one accelerator. The accelerator interface includes an accelerator instruction bus to convey instructions from the DSP processor to the accelerators. The DSP processor assigns an accelerator field in the instruction when the instruction is used to access the accelerators and further assigns an accelerator ID field in the instruction when the DSP processor selects a specific accelerator. The instruction also contains information to indicate a register address in the DSP processor and the command sent to the elected accelerator.

Abstract: A method for debugging electronic hardware includes providing a memory address, providing an expected value for data at the memory address, detecting an actual value for the data at the memory address when the memory address is accessed, determining whether the expected value for the data at the memory address is equal to the actual value for the data at the memory address, and halting execution of the hardware when it is determined that the expected value for the data at the memory address is not equal to the actual value for the data at the memory address.

Abstract: A system for interfacing a debugger, the debugger utilizing a test clock, with a system under debug, the system under debug utilizing one or more system clocks includes a test-clock unit, utilizing the test clock, connected in communication with the debugger, and one or more system-clock units, each of which having a corresponding one of the one or more system clocks, connected in communication with the system under debug and the test-clock unit. The one or more system-clock units utilize their corresponding system clock when communicating with the system under debug and utilize the test clock when communicating with the test-clock unit.