Patents by Inventor Ivor Barber
Ivor Barber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11393697Abstract: Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters.Type: GrantFiled: November 2, 2020Date of Patent: July 19, 2022Assignee: ADVANCED MICRO DEVICES, INCInventors: Rahul Agarwal, Milind S. Bhagavat, Ivor Barber, Venkatachalam Valliappan, Yuen Ting Cheng, Guan Sin Chok
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Publication number: 20210050223Abstract: Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters.Type: ApplicationFiled: November 2, 2020Publication date: February 18, 2021Inventors: RAHUL AGARWAL, MILIND S. BHAGAVAT, IVOR BARBER, VENKATACHALAM VALLIAPPAN, YUEN TING CHENG, GUAN SIN CHOK
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Patent number: 10825692Abstract: Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters.Type: GrantFiled: December 20, 2018Date of Patent: November 3, 2020Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Rahul Agarwal, Milind S. Bhagavat, Ivor Barber, Venkatachalam Valliappan, Yuen Ting Cheng, Guan Sin Chok
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Publication number: 20200203177Abstract: Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventors: Rahul Agarwal, Milind S. Bhagavat, Ivor Barber, Venkatachalam Valliappan, Yuen Ting Cheng, Guan Sin Chok
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Patent number: 10510721Abstract: Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.Type: GrantFiled: August 11, 2017Date of Patent: December 17, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Milind S. Bhagavat, Lei Fu, Ivor Barber, Chia-Ken Leong, Rahul Agarwal
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Publication number: 20190051633Abstract: Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.Type: ApplicationFiled: August 11, 2017Publication date: February 14, 2019Inventors: Milind S. Bhagavat, Lei Fu, Ivor Barber, Chia-Ken Leong, Rahul Agarwal
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Patent number: 7829424Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.Type: GrantFiled: July 16, 2008Date of Patent: November 9, 2010Assignee: LSI CorporationInventors: Leah Miller, Ivor Barber, Aritharan Thurairajaratnam
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Patent number: 7508062Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.Type: GrantFiled: March 11, 2005Date of Patent: March 24, 2009Assignee: LSI CorporationInventors: Leah Miller, Ivor Barber, Aritharan Thurairajaratnam
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Publication number: 20080272863Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.Type: ApplicationFiled: July 16, 2008Publication date: November 6, 2008Applicant: LSI LOGIC CORPORATIONInventors: LEAH MILLER, IVOR BARBER, ARITHARAN THURAIRAJARATNAM
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Patent number: 7173328Abstract: A semiconductor package having a substrate mounted die. The die configured having active circuit components and a top surface having bond pads electrically connected with circuitry of the die. The bond pads commonly being formed above active circuit components. The bond pads being electrically interconnected with wire bonds to establish intra-chip electrical connection between circuitry of the die. Methods of forming such packages are also disclosed.Type: GrantFiled: April 6, 2004Date of Patent: February 6, 2007Assignee: LSI Logic CorporationInventor: Ivor Barber
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Publication number: 20060202303Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.Type: ApplicationFiled: March 11, 2005Publication date: September 14, 2006Inventors: Leah Miller, Ivor Barber, Aritharan Thurairajaratnam
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Publication number: 20050224964Abstract: A semiconductor package having a substrate mounted die. The die configured having active circuit components and a top surface having bond pads electrically connected with circuitry of the die. The bond pads commonly being formed above active circuit components. The bond pads being electrically interconnected with wire bonds to establish intra-chip electrical connection between circuitry of the die. Methods of forming such packages are also disclosed.Type: ApplicationFiled: April 6, 2004Publication date: October 13, 2005Inventor: Ivor Barber
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Patent number: 5895968Abstract: A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wring board and is divided into electrically insulated conductive segments. Each of the conductive segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of bond fingers which serve to connect the semiconductor die to further external connections, such as signal connections. The present invention is especially advantageous in the fabrication of pin grid array (PGA) and ball grid array (BGA) type integrated circuit packages.Type: GrantFiled: October 24, 1997Date of Patent: April 20, 1999Inventor: Ivor Barber
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Patent number: 5741726Abstract: A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wring board and is divided into electrically insulated conductive segments. Each of the conductive segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of bond fingers which serve to connect the semiconductor die to further external connections, such as signal connections. The present invention is especially advantageous in the fabrication of pin grid array (PGA) and ball grid array (BGA) type integrated circuit packages.Type: GrantFiled: December 6, 1996Date of Patent: April 21, 1998Assignee: LSI Logic CorporationInventor: Ivor Barber
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Patent number: 5604161Abstract: A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wring board and is divided into electrically insulated conductive segments. Each of the conductive segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of bond fingers which serve to connect the semiconductor die to further external connections, such as signal connections. The present invention is especially advantageous in the fabrication of pin grid array (PGA) and ball grid array (BGA) type integrated circuit packages.Type: GrantFiled: June 6, 1995Date of Patent: February 18, 1997Assignee: LSI Logic CorporationInventor: Ivor Barber
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Patent number: 5545923Abstract: A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wring board and is divided into electrically insulated conductive segments. Each of the conductive segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of bond fingers which serve to connect the semiconductor die to further external connections, such as signal connections. The present invention is especially advantageous in the fabrication of pin grid array (PGA) and ball grid array (BGA) type integrated circuit packages.Type: GrantFiled: February 28, 1995Date of Patent: August 13, 1996Assignee: LSI Logic CorporationInventor: Ivor Barber