Patents by Inventor Iwao Sugiura

Iwao Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9985065
    Abstract: A solid-state imaging device includes: a photodiode formed to be segmented with respect to each pixel in a pixel area in which plural pixels are integrated on a light receiving surface of a semiconductor substrate; an insulator film formed on the semiconductor substrate to cover the photodiode; a recessed part formed with respect to each of the pixels in the insulator film in an upper part of the photodiode; a first light transmission layer of a siloxane resin formed to fill the recessed part and configure an optical waveguide in the pixel area; a second light transmission layer formed to configure an on-chip lens with respect to each of the pixels in the pixel area; and a guard ring formed to surround an outer circumference of the pixel area to partition an inner area containing the pixel area and an outer dicing area.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: May 29, 2018
    Assignee: Sony Corporation
    Inventors: Hideki Hirano, Akiko Ogino, Kenju Nishikido, Iwao Sugiura, Haruhiko Ajisawa, Ikuo Yoshihara
  • Publication number: 20160104736
    Abstract: A solid-state imaging device includes: a photodiode formed to be segmented with respect to each pixel in a pixel area in which plural pixels are integrated on a light receiving surface of a semiconductor substrate; an insulator film formed on the semiconductor substrate to cover the photodiode; a recessed part formed with respect to each of the pixels in the insulator film in an upper part of the photodiode; a first light transmission layer of a siloxane resin formed to fill the recessed part and configure an optical waveguide in the pixel area; a second light transmission layer formed to configure an on-chip lens with respect to each of the pixels in the pixel area; and a guard ring formed to surround an outer circumference of the pixel area to partition an inner area containing the pixel area and an outer dicing area.
    Type: Application
    Filed: September 11, 2015
    Publication date: April 14, 2016
    Inventors: Hideki Hirano, Akiko Ogino, Kenju Nishikido, Iwao Sugiura, Haruhiko Ajisawa, Ikuo Yoshihara
  • Patent number: 9171877
    Abstract: A solid-state imaging device includes: a photodiode formed to be segmented with respect to each pixel in a pixel area in which plural pixels are integrated on a light receiving surface of a semiconductor substrate; an insulator film formed on the semiconductor substrate to cover the photodiode; a recessed part formed with respect to each of the pixels in the insulator film in an upper part of the photodiode; a first light transmission layer of a siloxane resin formed to fill the recessed part and configure an optical waveguide in the pixel area; a second light transmission layer formed to configure an on-chip lens with respect to each of the pixels in the pixel area; and a guard ring formed to surround an outer circumference of the pixel area to partition an inner area containing the pixel area and an outer dicing area.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: October 27, 2015
    Assignee: Sony Corporation
    Inventors: Hideki Hirano, Akiko Ogino, Kenju Nishikido, Iwao Sugiura, Haruhiko Ajisawa, Ikuo Yoshihara
  • Patent number: 9099534
    Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: August 4, 2015
    Assignee: Sony Corporation
    Inventors: Kazuto Watanabe, Atsushi Matsushita, Hiroshi Horikoshi, Iwao Sugiura, Yuuji Nishimura, Syota Yamabata
  • Publication number: 20140329353
    Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.
    Type: Application
    Filed: June 30, 2014
    Publication date: November 6, 2014
    Applicant: SONY CORPORATION
    Inventors: Kazuto Watanabe, Atsushi Matsushita, Hiroshi Horikoshi, Iwao Sugiura, Yuuji Nishimura, Syota Yamabata
  • Patent number: 8786089
    Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: July 22, 2014
    Assignee: Sony Corporation
    Inventors: Kazuto Watanabe, Atsushi Matsushita, Hiroshi Horikoshi, Iwao Sugiura, Yuuji Nishimura, Syota Yamabata
  • Patent number: 8759933
    Abstract: Disclosed herein is a solid-state image pickup element, including: a semiconductor substrate; a pixel portion which is formed on the semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion portion are arranged; an insulating layer formed on the semiconductor substrate so as to cover the photoelectric conversion portion; a hole portion formed in the insulating layer and above the photoelectric conversion portion; a silicon nitride layer formed so as to cover a bottom surface and a side surface of the hole portion; and a buried layer formed on the silicon nitride layer, wherein the silicon nitride layer is formed so as to contain a silicon nitride formed by utilizing an atomic layer deposition method.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: June 24, 2014
    Assignee: Sony Corporation
    Inventors: Yoshinori Toumiya, Kiyotaka Tabuchi, Yasuyuki Shiga, Iwao Sugiura, Naoyuki Miyashita, Masanori Iwasaki, Katsunori Kokubun, Tomohiro Yamazaki
  • Patent number: 8373786
    Abstract: A solid-state imaging device has: an imaging region in which a plurality of pixels each having a photoelectric conversion element are arranged, and a color filter. The color filter includes: filter components of a first color (2G), filter components of a second color (2R) formed by self-alignment and each being surrounded by the filter components of the first color (2G), and filter components of a third color (2B) formed by self-alignment and each being surrounded by the filter components of the first color (2G).
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: February 12, 2013
    Assignee: Sony Corporation
    Inventors: Yoichi Otsuka, Yoshiyuki Enomoto, Kazunori Nagahata, Tadayuki Kimura, Toshihiko Hayashi, Kenichi Aoyagi, Kiyotaka Tabuchi, Iwao Sugiura, Kensaku Maeda
  • Publication number: 20120211879
    Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 23, 2012
    Applicant: Sony Corporation
    Inventors: Kazuto WATANABE, Atsushi MATSUSHITA, Hiroshi HORIKOSHI, Iwao SUGIURA, Yuuji NISHIMURA, Syota YAMABATA
  • Publication number: 20110024857
    Abstract: Disclosed herein is a solid-state image pickup element, including: a semiconductor substrate; a pixel portion which is formed on the semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion portion are arranged; an insulating layer formed on the semiconductor substrate so as to cover the photoelectric conversion portion; a hole portion formed in the insulating layer and above the photoelectric conversion portion; a silicon nitride layer formed so as to cover a bottom surface and a side surface of the hole portion; and a buried layer formed on the silicon nitride layer, wherein the silicon nitride layer is formed so as to contain a silicon nitride formed by utilizing an atomic layer deposition method.
    Type: Application
    Filed: May 27, 2010
    Publication date: February 3, 2011
    Applicant: SONY CORPORATION
    Inventors: Yoshinori Toumiya, Kiyotaka Tabuchi, Yasuyuki Shiga, Iwao Sugiura, Naoyuki Miyashita, Masanori Iwasaki, Katsunori Kokubun, Tomohiro Yamazaki
  • Publication number: 20100155582
    Abstract: A solid-state imaging device includes: a photodiode formed to be segmented with respect to each pixel in a pixel area in which plural pixels are integrated on a light receiving surface of a semiconductor substrate; an insulator film formed on the semiconductor substrate to cover the photodiode; a recessed part formed with respect to each of the pixels in the insulator film in an upper part of the photodiode; a first light transmission layer of a siloxane resin formed to fill the recessed part and configure an optical waveguide in the pixel area; a second light transmission layer formed to configure an on-chip lens with respect to each of the pixels in the pixel area; and a guard ring formed to surround an outer circumference of the pixel area to partition an inner area containing the pixel area and an outer dicing area.
    Type: Application
    Filed: December 9, 2009
    Publication date: June 24, 2010
    Applicant: SONY CORPORATION
    Inventors: Hideki HIRANO, Akiko OGINO, Kenju NISHIKIDO, Iwao SUGIURA, Haruhiko AJISAWA, Ikuo YOSHIHARA
  • Patent number: 7642650
    Abstract: A semiconductor device includes a first multilayer interconnection structure formed on a substrate and a second multilayer interconnection structure formed on the first multilayer interconnection structure, wherein the first multilayer interconnection structure includes a pillar extending from a surface of the substrate and reaching at least the second multilayer interconnection structure.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: January 5, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Iwao Sugiura, Takahisa Namiki, Yoshihiro Matsuoka
  • Publication number: 20090303359
    Abstract: A solid-state imaging device has: an imaging region in which a plurality of pixels each having a photoelectric conversion element are arranged, and a color filter. The color filter includes: filter components of a first color (2G), filter components of a second color (2R) formed by self-alignment and each being surrounded by the filter components of the first color (2G), and filter components of a third color (2B) formed by self-alignment and each being surrounded by the filter components of the first color (2G).
    Type: Application
    Filed: May 1, 2009
    Publication date: December 10, 2009
    Applicant: Sony Corporation
    Inventors: Yoichi OTSUKA, Yoshiyuki ENOMOTO, Kazunori NAGAHATA, Tadayuki KIMURA, Toshihiko HAYASHI, Kenichi AOYAGI, Kiyotaka TABUCHI, Iwao SUGIURA, Kensaku MAEDA
  • Patent number: 7483818
    Abstract: A structural analysis program which enables easy structural analysis in accordance with a finite element method based on data representing a two-dimensional shape. A two-dimensional model of a structure is produced in response to a manipulation input which designates a material arrangement pattern and a thickness of each layer of the structure. A three-dimensional model is produced by adding the designated thickness of each layer to the material arrangement pattern of the layer so as to make the material arrangement pattern three-dimensional and stacking the three-dimensionalized material arrangement pattern of each layer. A finite element model is produced by dividing the three-dimensional model into a plurality of voxels. The computer performs structural analysis based on the produced finite element model. Thereby, an analysis result of a multilayer structure defined by the two-dimensional model is obtained.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: January 27, 2009
    Assignee: Fujitsu Nagano Systems Engineering Limited
    Inventors: Makoto Amakai, Iwao Sugiura, Takanori Negishi, Yasuhiro Kawashima, Gen Kamurai, Kazuyuki Imamura
  • Patent number: 7235866
    Abstract: A low dielectric film forming material contains siloxane resin and polycarbosilane dissolved in solvent. By using this solution, a low dielectric film is formed which contains siloxane resin and polycarbosilane bonded to the siloxane resin. Material of a low dielectric film is provided which is suitable for inter-level insulating film material. A semiconductor device is also provided which has a low dielectric constant film and high reliability.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: June 26, 2007
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Nakata, Shun-ichi Fukuyama, Katsumi Suzuki, Ei Yano, Tamotsu Owada, Iwao Sugiura
  • Patent number: 7170177
    Abstract: A disclosed semiconductor apparatus includes a substrate, a first insulating layer formed on the substrate, the first insulating layer including a Cu wiring part, and a second insulating layer formed on the substrate, the second insulating layer including a Cu via plug part electrically connected to the Cu wiring part. The first insulating layer is a porous insulating film having an elastic modulus of 5 GPa or more and a hardness of 0.6 GPa or more, and the second insulating layer has an elastic modulus of no less than 10 GPa and a hardness no less than 1 GPa.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: January 30, 2007
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Nakata, Katsumi Suzuki, Iwao Sugiura, Ei Yano
  • Publication number: 20060022357
    Abstract: A low dielectric film forming material contains siloxane resin and polycarbosilane dissolved in solvent. By using this solution, a low dielectric film is formed which contains siloxane resin and polycarbosilane bonded to the siloxane resin. Material of a low dielectric film is provided which is suitable for inter-level insulating film material. A semiconductor device is also provided which has a low dielectric constant film and high reliability.
    Type: Application
    Filed: August 17, 2005
    Publication date: February 2, 2006
    Applicant: Fujitsu Limited
    Inventors: Yoshihiro Nakata, Shun-ichi Fukuyama, Katsumi Suzuki, Ei Yano, Tamotsu Owada, Iwao Sugiura
  • Publication number: 20050253271
    Abstract: A disclosed semiconductor apparatus includes a substrate, a first insulating layer formed on the substrate, the first insulating layer including a Cu wiring part, and a second insulating layer formed on the substrate, the second insulating layer including a Cu via plug part electrically connected to the Cu wiring part. The first insulating layer is a porous insulating film having an elastic modulus of 5 GPa or more and a hardness of 0.6 GPa or more, and the second insulating layer has an elastic modulus of no less than 10 GPa and a hardness no less than 1 GPa.
    Type: Application
    Filed: April 27, 2005
    Publication date: November 17, 2005
    Inventors: Yoshihiro Nakata, Katsumi Suzuki, Iwao Sugiura, Ei Yano
  • Patent number: 6958525
    Abstract: A low dielectric film forming material contains siloxane resin and polycarbosilane dissolved in solvent. By using this solution, a low dielectric film is formed which contains siloxane resin and polycarbosilane bonded to the siloxane resin. Material of a low dielectric film is provided which is suitable for inter-level insulating film material. A semiconductor device is also provided which has a low dielectric constant film and high reliability.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: October 25, 2005
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Nakata, Shun-ichi Fukuyama, Katsumi Suzuki, Ei Yano, Tamotsu Owada, Iwao Sugiura
  • Publication number: 20040164418
    Abstract: A semiconductor device includes a first multilayer interconnection structure formed on a substrate and a second multilayer interconnection structure formed on the first multilayer interconnection structure, wherein the first multilayer interconnection structure includes a pillar extending from a surface of the substrate and reaching at least the second multilayer interconnection structure.
    Type: Application
    Filed: February 19, 2004
    Publication date: August 26, 2004
    Applicant: Fujitsu Limited
    Inventors: Iwao Sugiura, Takahisa Namiki, Yoshihiro Matsuoka