Patents by Inventor Iwao Sugiura
Iwao Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9985065Abstract: A solid-state imaging device includes: a photodiode formed to be segmented with respect to each pixel in a pixel area in which plural pixels are integrated on a light receiving surface of a semiconductor substrate; an insulator film formed on the semiconductor substrate to cover the photodiode; a recessed part formed with respect to each of the pixels in the insulator film in an upper part of the photodiode; a first light transmission layer of a siloxane resin formed to fill the recessed part and configure an optical waveguide in the pixel area; a second light transmission layer formed to configure an on-chip lens with respect to each of the pixels in the pixel area; and a guard ring formed to surround an outer circumference of the pixel area to partition an inner area containing the pixel area and an outer dicing area.Type: GrantFiled: September 11, 2015Date of Patent: May 29, 2018Assignee: Sony CorporationInventors: Hideki Hirano, Akiko Ogino, Kenju Nishikido, Iwao Sugiura, Haruhiko Ajisawa, Ikuo Yoshihara
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Publication number: 20160104736Abstract: A solid-state imaging device includes: a photodiode formed to be segmented with respect to each pixel in a pixel area in which plural pixels are integrated on a light receiving surface of a semiconductor substrate; an insulator film formed on the semiconductor substrate to cover the photodiode; a recessed part formed with respect to each of the pixels in the insulator film in an upper part of the photodiode; a first light transmission layer of a siloxane resin formed to fill the recessed part and configure an optical waveguide in the pixel area; a second light transmission layer formed to configure an on-chip lens with respect to each of the pixels in the pixel area; and a guard ring formed to surround an outer circumference of the pixel area to partition an inner area containing the pixel area and an outer dicing area.Type: ApplicationFiled: September 11, 2015Publication date: April 14, 2016Inventors: Hideki Hirano, Akiko Ogino, Kenju Nishikido, Iwao Sugiura, Haruhiko Ajisawa, Ikuo Yoshihara
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Patent number: 9171877Abstract: A solid-state imaging device includes: a photodiode formed to be segmented with respect to each pixel in a pixel area in which plural pixels are integrated on a light receiving surface of a semiconductor substrate; an insulator film formed on the semiconductor substrate to cover the photodiode; a recessed part formed with respect to each of the pixels in the insulator film in an upper part of the photodiode; a first light transmission layer of a siloxane resin formed to fill the recessed part and configure an optical waveguide in the pixel area; a second light transmission layer formed to configure an on-chip lens with respect to each of the pixels in the pixel area; and a guard ring formed to surround an outer circumference of the pixel area to partition an inner area containing the pixel area and an outer dicing area.Type: GrantFiled: December 9, 2009Date of Patent: October 27, 2015Assignee: Sony CorporationInventors: Hideki Hirano, Akiko Ogino, Kenju Nishikido, Iwao Sugiura, Haruhiko Ajisawa, Ikuo Yoshihara
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Patent number: 9099534Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.Type: GrantFiled: June 30, 2014Date of Patent: August 4, 2015Assignee: Sony CorporationInventors: Kazuto Watanabe, Atsushi Matsushita, Hiroshi Horikoshi, Iwao Sugiura, Yuuji Nishimura, Syota Yamabata
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Publication number: 20140329353Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.Type: ApplicationFiled: June 30, 2014Publication date: November 6, 2014Applicant: SONY CORPORATIONInventors: Kazuto Watanabe, Atsushi Matsushita, Hiroshi Horikoshi, Iwao Sugiura, Yuuji Nishimura, Syota Yamabata
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Patent number: 8786089Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.Type: GrantFiled: January 26, 2012Date of Patent: July 22, 2014Assignee: Sony CorporationInventors: Kazuto Watanabe, Atsushi Matsushita, Hiroshi Horikoshi, Iwao Sugiura, Yuuji Nishimura, Syota Yamabata
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Patent number: 8759933Abstract: Disclosed herein is a solid-state image pickup element, including: a semiconductor substrate; a pixel portion which is formed on the semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion portion are arranged; an insulating layer formed on the semiconductor substrate so as to cover the photoelectric conversion portion; a hole portion formed in the insulating layer and above the photoelectric conversion portion; a silicon nitride layer formed so as to cover a bottom surface and a side surface of the hole portion; and a buried layer formed on the silicon nitride layer, wherein the silicon nitride layer is formed so as to contain a silicon nitride formed by utilizing an atomic layer deposition method.Type: GrantFiled: May 27, 2010Date of Patent: June 24, 2014Assignee: Sony CorporationInventors: Yoshinori Toumiya, Kiyotaka Tabuchi, Yasuyuki Shiga, Iwao Sugiura, Naoyuki Miyashita, Masanori Iwasaki, Katsunori Kokubun, Tomohiro Yamazaki
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Patent number: 8373786Abstract: A solid-state imaging device has: an imaging region in which a plurality of pixels each having a photoelectric conversion element are arranged, and a color filter. The color filter includes: filter components of a first color (2G), filter components of a second color (2R) formed by self-alignment and each being surrounded by the filter components of the first color (2G), and filter components of a third color (2B) formed by self-alignment and each being surrounded by the filter components of the first color (2G).Type: GrantFiled: May 1, 2009Date of Patent: February 12, 2013Assignee: Sony CorporationInventors: Yoichi Otsuka, Yoshiyuki Enomoto, Kazunori Nagahata, Tadayuki Kimura, Toshihiko Hayashi, Kenichi Aoyagi, Kiyotaka Tabuchi, Iwao Sugiura, Kensaku Maeda
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Publication number: 20120211879Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.Type: ApplicationFiled: January 26, 2012Publication date: August 23, 2012Applicant: Sony CorporationInventors: Kazuto WATANABE, Atsushi MATSUSHITA, Hiroshi HORIKOSHI, Iwao SUGIURA, Yuuji NISHIMURA, Syota YAMABATA
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Publication number: 20110024857Abstract: Disclosed herein is a solid-state image pickup element, including: a semiconductor substrate; a pixel portion which is formed on the semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion portion are arranged; an insulating layer formed on the semiconductor substrate so as to cover the photoelectric conversion portion; a hole portion formed in the insulating layer and above the photoelectric conversion portion; a silicon nitride layer formed so as to cover a bottom surface and a side surface of the hole portion; and a buried layer formed on the silicon nitride layer, wherein the silicon nitride layer is formed so as to contain a silicon nitride formed by utilizing an atomic layer deposition method.Type: ApplicationFiled: May 27, 2010Publication date: February 3, 2011Applicant: SONY CORPORATIONInventors: Yoshinori Toumiya, Kiyotaka Tabuchi, Yasuyuki Shiga, Iwao Sugiura, Naoyuki Miyashita, Masanori Iwasaki, Katsunori Kokubun, Tomohiro Yamazaki
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Publication number: 20100155582Abstract: A solid-state imaging device includes: a photodiode formed to be segmented with respect to each pixel in a pixel area in which plural pixels are integrated on a light receiving surface of a semiconductor substrate; an insulator film formed on the semiconductor substrate to cover the photodiode; a recessed part formed with respect to each of the pixels in the insulator film in an upper part of the photodiode; a first light transmission layer of a siloxane resin formed to fill the recessed part and configure an optical waveguide in the pixel area; a second light transmission layer formed to configure an on-chip lens with respect to each of the pixels in the pixel area; and a guard ring formed to surround an outer circumference of the pixel area to partition an inner area containing the pixel area and an outer dicing area.Type: ApplicationFiled: December 9, 2009Publication date: June 24, 2010Applicant: SONY CORPORATIONInventors: Hideki HIRANO, Akiko OGINO, Kenju NISHIKIDO, Iwao SUGIURA, Haruhiko AJISAWA, Ikuo YOSHIHARA
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Patent number: 7642650Abstract: A semiconductor device includes a first multilayer interconnection structure formed on a substrate and a second multilayer interconnection structure formed on the first multilayer interconnection structure, wherein the first multilayer interconnection structure includes a pillar extending from a surface of the substrate and reaching at least the second multilayer interconnection structure.Type: GrantFiled: February 19, 2004Date of Patent: January 5, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Iwao Sugiura, Takahisa Namiki, Yoshihiro Matsuoka
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Publication number: 20090303359Abstract: A solid-state imaging device has: an imaging region in which a plurality of pixels each having a photoelectric conversion element are arranged, and a color filter. The color filter includes: filter components of a first color (2G), filter components of a second color (2R) formed by self-alignment and each being surrounded by the filter components of the first color (2G), and filter components of a third color (2B) formed by self-alignment and each being surrounded by the filter components of the first color (2G).Type: ApplicationFiled: May 1, 2009Publication date: December 10, 2009Applicant: Sony CorporationInventors: Yoichi OTSUKA, Yoshiyuki ENOMOTO, Kazunori NAGAHATA, Tadayuki KIMURA, Toshihiko HAYASHI, Kenichi AOYAGI, Kiyotaka TABUCHI, Iwao SUGIURA, Kensaku MAEDA
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Patent number: 7483818Abstract: A structural analysis program which enables easy structural analysis in accordance with a finite element method based on data representing a two-dimensional shape. A two-dimensional model of a structure is produced in response to a manipulation input which designates a material arrangement pattern and a thickness of each layer of the structure. A three-dimensional model is produced by adding the designated thickness of each layer to the material arrangement pattern of the layer so as to make the material arrangement pattern three-dimensional and stacking the three-dimensionalized material arrangement pattern of each layer. A finite element model is produced by dividing the three-dimensional model into a plurality of voxels. The computer performs structural analysis based on the produced finite element model. Thereby, an analysis result of a multilayer structure defined by the two-dimensional model is obtained.Type: GrantFiled: May 31, 2002Date of Patent: January 27, 2009Assignee: Fujitsu Nagano Systems Engineering LimitedInventors: Makoto Amakai, Iwao Sugiura, Takanori Negishi, Yasuhiro Kawashima, Gen Kamurai, Kazuyuki Imamura
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Patent number: 7235866Abstract: A low dielectric film forming material contains siloxane resin and polycarbosilane dissolved in solvent. By using this solution, a low dielectric film is formed which contains siloxane resin and polycarbosilane bonded to the siloxane resin. Material of a low dielectric film is provided which is suitable for inter-level insulating film material. A semiconductor device is also provided which has a low dielectric constant film and high reliability.Type: GrantFiled: August 17, 2005Date of Patent: June 26, 2007Assignee: Fujitsu LimitedInventors: Yoshihiro Nakata, Shun-ichi Fukuyama, Katsumi Suzuki, Ei Yano, Tamotsu Owada, Iwao Sugiura
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Patent number: 7170177Abstract: A disclosed semiconductor apparatus includes a substrate, a first insulating layer formed on the substrate, the first insulating layer including a Cu wiring part, and a second insulating layer formed on the substrate, the second insulating layer including a Cu via plug part electrically connected to the Cu wiring part. The first insulating layer is a porous insulating film having an elastic modulus of 5 GPa or more and a hardness of 0.6 GPa or more, and the second insulating layer has an elastic modulus of no less than 10 GPa and a hardness no less than 1 GPa.Type: GrantFiled: April 27, 2005Date of Patent: January 30, 2007Assignee: Fujitsu LimitedInventors: Yoshihiro Nakata, Katsumi Suzuki, Iwao Sugiura, Ei Yano
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Publication number: 20060022357Abstract: A low dielectric film forming material contains siloxane resin and polycarbosilane dissolved in solvent. By using this solution, a low dielectric film is formed which contains siloxane resin and polycarbosilane bonded to the siloxane resin. Material of a low dielectric film is provided which is suitable for inter-level insulating film material. A semiconductor device is also provided which has a low dielectric constant film and high reliability.Type: ApplicationFiled: August 17, 2005Publication date: February 2, 2006Applicant: Fujitsu LimitedInventors: Yoshihiro Nakata, Shun-ichi Fukuyama, Katsumi Suzuki, Ei Yano, Tamotsu Owada, Iwao Sugiura
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Publication number: 20050253271Abstract: A disclosed semiconductor apparatus includes a substrate, a first insulating layer formed on the substrate, the first insulating layer including a Cu wiring part, and a second insulating layer formed on the substrate, the second insulating layer including a Cu via plug part electrically connected to the Cu wiring part. The first insulating layer is a porous insulating film having an elastic modulus of 5 GPa or more and a hardness of 0.6 GPa or more, and the second insulating layer has an elastic modulus of no less than 10 GPa and a hardness no less than 1 GPa.Type: ApplicationFiled: April 27, 2005Publication date: November 17, 2005Inventors: Yoshihiro Nakata, Katsumi Suzuki, Iwao Sugiura, Ei Yano
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Patent number: 6958525Abstract: A low dielectric film forming material contains siloxane resin and polycarbosilane dissolved in solvent. By using this solution, a low dielectric film is formed which contains siloxane resin and polycarbosilane bonded to the siloxane resin. Material of a low dielectric film is provided which is suitable for inter-level insulating film material. A semiconductor device is also provided which has a low dielectric constant film and high reliability.Type: GrantFiled: May 30, 2003Date of Patent: October 25, 2005Assignee: Fujitsu LimitedInventors: Yoshihiro Nakata, Shun-ichi Fukuyama, Katsumi Suzuki, Ei Yano, Tamotsu Owada, Iwao Sugiura
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Publication number: 20040164418Abstract: A semiconductor device includes a first multilayer interconnection structure formed on a substrate and a second multilayer interconnection structure formed on the first multilayer interconnection structure, wherein the first multilayer interconnection structure includes a pillar extending from a surface of the substrate and reaching at least the second multilayer interconnection structure.Type: ApplicationFiled: February 19, 2004Publication date: August 26, 2004Applicant: Fujitsu LimitedInventors: Iwao Sugiura, Takahisa Namiki, Yoshihiro Matsuoka