Patents by Inventor Iwao Takiguchi

Iwao Takiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8069361
    Abstract: A determining unit determines the state of the microprocessor. A setting unit sets a power supply voltage to be supplied to the microprocessor according to the state of the microprocessor determined by the determining unit. A power supply circuit supplies the power supply voltage set by the setting unit, to the microprocessor via a power supply line. The determining unit determines repeatedly the state of the microprocessor at preset timing, and the setting unit resets the power supply voltage every time the determination is performed by the determining unit.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: November 29, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Tetsuji Tamura, Iwao Takiguchi, Yosuke Muraki, Toshiyuki Hiroi, Koji Inoue, Makoto Aikawa
  • Patent number: 8068940
    Abstract: In a control stack included in a software, a control execution unit allows a receiving unit to receive the temperatures of a main processor and a graphic processor. When it determines based on these temperatures that a thermal error has occurred, the control execution unit allows a type acquisition unit to acquire the type of an application running currently. The control execution unit then performs hardware control processing for adjusting the operation of hardware, and software control processing for changing the operation of an application, so as to control the state of heat generation in the hardware. In the software control processing, the control execution unit acquires, from a reaction table, a control method corresponding to the combination of the part where a thermal error has occurred and the type of the running application, and provides control according to the acquired control method.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: November 29, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Kenichi Adachi, Tetsuji Tamura, Iwao Takiguchi
  • Patent number: 8051304
    Abstract: In a power supply apparatus for supplying a target power supply voltage to a microprocessor, a system controller sets the target power supply voltage to be supplied to the microprocessor based on a voltage configuration signal outputted from the microprocessor and outputs a voltage setting signal corresponding to the target power supply voltage. The regulator circuit generates the target power supply voltage set by the system controller based on the voltage setting signal outputted from the system controller and supplies the voltage to the microprocessor 10. The system controller acquires the conditions of the microprocessor, such as the operating time and temperature of the microprocessor and the amount of computation in the microprocessor, and reflects the acquired conditions on the setting of the power supply voltage.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: November 1, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Iwao Takiguchi, Kazuaki Mitsui, Tetsuji Tamura, Atsuhiko Imai
  • Patent number: 7973434
    Abstract: An electromotive cooling head includes a substrate, an N-pole magnet, and an S-pole magnet, and kept in intimate contact with the backside of the semiconductor integrated circuit so as to cover it. The substrate has a fluid channel having a micro-channel structure, through which a conductive fluid flows. An anode and a cathode are disposed to sandwich the fluid channel. The conductive fluid interacts with a magnetic field to thereby induce an electromotive force between the anode and the cathode. A circuit includes, on its backside, a power supply voltage terminal and a ground terminal, and is driven by the electromotive force induced in the electromotive cooling head.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: July 5, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Kazuaki Yazawa, Iwao Takiguchi
  • Patent number: 7954101
    Abstract: This task management method includes dividing a unit time of processing into a reserved band for guaranteeing real-timeness and a non-reserved band not for guaranteeing real-timeness, and skipping a task to be executed in the non-reserved band as appropriate when processor throughput falls. That is, when the operating frequency of the processor is lowered in order to suppress heat generation, the real-timeness of tasks to be executed in the reserved band is guaranteed at the expense of processing the task to be executed in the non-reserved band in a best-efforts fashion.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: May 31, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Kenichi Adachi, Kazuaki Yazawa, Iwao Takiguchi, Atsuhiko Imai, Tetsuji Tamura
  • Patent number: 7917347
    Abstract: Mechanisms for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Makoto Aikawa, Jonathan J. DeMent, Sang H. Dhong, Brian K. Flachs, Gilles Gervais, Iwao Takiguchi, Tetsuji Tamura
  • Patent number: 7831842
    Abstract: A heat generation amount estimation unit acquires the number of sub processors currently in operation, acquires the current operating frequency, and estimates the amount of heat generation after a period ?t. A temperature control unit estimates the temperature after the period ?t based on the current temperature input from a temperature sensor and the amount of heat generation estimated, and compares it with a predetermined threshold temperature. If the predetermined threshold temperature is reached, the temperature control unit acquires the number of sub processors available in parallel after the period ?t from a task management unit, and consults a performance table to determine which operation point to shift to. A sub processor control unit and a frequency control unit switch to the number of sub processors in operation and the operating frequency accordingly. The performance table lists possible operation points in order of performance.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: November 9, 2010
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Kenichi Adachi, Kazuaki Yazawa, Iwao Takiguchi, Atsuhiko Imai, Tetsuji Tamura
  • Patent number: 7716516
    Abstract: A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: May 11, 2010
    Assignees: Sony Computer Entertainment Inc., International Business Machines Corporation, Toshiba America Electronic Components, Inc.
    Inventors: Yosuke Muraki, Tetsuji Tamura, Iwao Takiguchi, Makoto Aikawa, Eskinder Hailu, Byron Lee Krauter, Stephen Douglas Weitzel, Jieming Qi, Kazuhiko Miki, David William Boerstler, Gilles Gervais, Kirk David Peterson, Robert Walter Berry, Jr., Sang Hoo Dhong
  • Publication number: 20090292404
    Abstract: A control execution unit (114) of a control stack (110) contained in a software stack causes a receiving unit (112) to receive the temperatures of a main processor and a graphic processor. When it is discriminated on the basis of those temperatures that a thermal error has occurred, the control execution unit (114) causes a class acquisition unit (116) to acquire the class of an active application. Moreover, the control execution unit (114) executes a hardware control operation to adjust the action of a hardware and a software control operation to change the action contents of the application, thereby to control the heat generation state of the hardware. When the software control operation is to be executed, a control method according to the combination of a portion, at which the thermal error has occurred, and the kind of the active application is acquired from a reaction table (118), thereby to control the software control operation by the control method acquired.
    Type: Application
    Filed: July 20, 2006
    Publication date: November 26, 2009
    Applicant: SONY COMPUTER ENTERTAINMENT INC.
    Inventors: Kenichi Adachi, Tetsuji Tamura, Iwao Takiguchi
  • Publication number: 20090228727
    Abstract: A determining unit determines the state of the microprocessor. A setting unit sets a power supply voltage to be supplied to the microprocessor according to the state of the microprocessor determined by the determining unit. A power supply circuit supplies the power supply voltage set by the setting unit, to the microprocessor via a power supply line. The determining unit determines repeatedly the state of the microprocessor at preset timing, and the setting unit resets the power supply voltage every time the determination is performed by the determining unit.
    Type: Application
    Filed: November 20, 2006
    Publication date: September 10, 2009
    Applicant: SONY COMPUTER ENTERTAINMENT INC.
    Inventors: Tetsuji Tamura, Iwao Takiguchi, Yosuke Muraki, Toshiyuki Hiroi, Koji Inoue, Makoto Aikawa
  • Publication number: 20090222251
    Abstract: A design structure for a integrated circuit interfacing system may be embodied in a machine readable medium for designing, manufacturing or testing a integrated circuit. In one embodiment, the design structure specifies an integrated circuit that includes multiple interfaces. The design structure may specify that each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. The design structure may also specify a bridge circuit on the integrated circuit that switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.
    Type: Application
    Filed: December 31, 2008
    Publication date: September 3, 2009
    Applicant: International Business Machines Corporation
    Inventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack Wayne Riley, Shoji Sawamura, Iwao Takiguchi
  • Patent number: 7535020
    Abstract: Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional blocks, preferably in the same relative location on each of the duplicate functional blocks, and preferably at a hotspot. One embodiment also includes thermal sensors on one or more functional blocks of other types in the integrated circuit. One embodiment includes a thermal sensor positioned at a cool spot, such as at the edge of the integrated circuit chip. Each of the thermal sensors may have ports to enable power and ground connections or data connections between the sensors and external components or devices.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: May 19, 2009
    Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corporation, Sony Computer Entertainment Inc.
    Inventors: Munehiro Yoshida, Daniel Stasiak, Michael F. Wang, Charles R. Johns, Hiroki Kihara, Tetsuji Tamura, Kazuaki Yazawa, Iwao Takiguchi
  • Publication number: 20090112550
    Abstract: A system and method for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Inventors: Makoto Aikawa, Jonathan J. DeMent, Sang H. Dhong, Brian K. Flachs, Gilles Gervais, Iwao Takiguchi, Tetsuji Tamura
  • Patent number: 7520669
    Abstract: A temperature sensor measures a temperature of a certain location inside a processor. An overall heat amount measurement unit measures the overall amount of heat of the processor. A temperature estimation unit estimates the temperatures of a plurality of hot spots occurring in the processor based on the temperature of the certain location detected by the temperature sensor, and determines the maximum temperature of the processor. The temperature estimation unit switches between maximum load temperature estimation coefficients and individual load temperature estimation coefficients stored in a storing unit for reference, depending on the overall amount of heat of the processor, and applies them to a temperature estimation function(s) for converting the sensor temperature into the temperatures of the hot spots.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: April 21, 2009
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Kazuaki Yazawa, Iwao Takiguchi, Atsuhiko Imai, Tetsuji Tamura, Kenichi Adachi
  • Publication number: 20090037752
    Abstract: In a power supply apparatus for supplying a target power supply voltage to a microprocessor, a system controller sets the target power supply voltage to be supplied to the microprocessor based on a voltage configuration signal outputted from the microprocessor and outputs a voltage setting signal corresponding to the target power supply voltage. The regulator circuit generates the target power supply voltage set by the system controller based on the voltage setting signal outputted from the system controller and supplies the voltage to the microprocessor 10. The system controller acquires the conditions of the microprocessor, such as the operating time and temperature of the microprocessor and the amount of computation in the microprocessor, and reflects the acquired conditions on the setting of the power supply voltage.
    Type: Application
    Filed: April 24, 2006
    Publication date: February 5, 2009
    Applicant: SONY COMPUTER ENTERTAINMENT INC.
    Inventors: Iwao Takiguchi, Kazuaki Mitsui, Tetsuji Tamura, Atsuhiko Imai
  • Patent number: 7486096
    Abstract: In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Sang H. Dhong, Brian Flachs, Gilles Gervais, Charles R. Johns, Brad W. Michael, Makoto Aikawa, Iwao Takiguchi, Tetsuji Tamura
  • Publication number: 20080189090
    Abstract: A system and method for determining a guard band for an operating voltage of an integrated circuit device are provided. The system and method provide a mechanism for calculating the guard band based on a comparison of simulated noise obtained from a simulation of the integrated circuit device using a worst case waveform stimuli with simulated or measured power supply noise of a workload/test pattern that may be achieved using testing equipment. A scaling factor for the guard band is determined by comparing results of a simulation of a workload/test pattern with measured results of the workload/test pattern as applied to a hardware implementation of the integrated circuit device. This scaling factor is applied to a difference between the noise generated through simulation of the workload/test pattern and the noise generated through simulation of the worst case current waveform to generate a guard band value.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 7, 2008
    Inventors: Makoto Aikawa, Sang H. Dhong, Brian Flachs, Gilles Gervais, Yoichi Nishino, Iwao Takiguchi, Tetsuji Tamura, Yaping Zhou
  • Publication number: 20080147901
    Abstract: In one embodiment, the disclosed methodology and apparatus involves an integrated circuit that includes multiple interfaces. Each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. A bridge circuit on the integrated circuit switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.
    Type: Application
    Filed: October 31, 2006
    Publication date: June 19, 2008
    Applicant: IBM Corporation
    Inventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack Wayne Riley, Shoji Sawamura, Iwao Takiguchi
  • Publication number: 20080100328
    Abstract: In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 1, 2008
    Applicant: IBM Corporation
    Inventors: Sang H. Dhong, Brian Flachs, Gilles Gervais, Charles R. Johns, Brad W. Michael, Makoto Aikawa, Iwao Takiguchi, Tetsuji Tamura
  • Publication number: 20080043807
    Abstract: A temperature sensor measures a temperature of a certain location inside a processor. An overall heat amount measurement unit measures the overall amount of heat of the processor. A temperature estimation unit estimates the temperatures of a plurality of hot spots occurring in the processor based on the temperature of the certain location detected by the temperature sensor, and determines the maximum temperature of the processor. The temperature estimation unit switches between maximum load temperature estimation coefficients and individual load temperature estimation coefficients stored in a storing unit for reference, depending on the overall amount of heat of the processor, and applies them to a temperature estimation function(s) for converting the sensor temperature into the temperatures of the hot spots.
    Type: Application
    Filed: April 26, 2005
    Publication date: February 21, 2008
    Applicant: Sony Computer Entertainment Inc.
    Inventors: Kazuaki Yazawa, Iwao Takiguchi, Atsuhiko Imai, Tetsuji Tamura, Kenichi Adachi