Patents by Inventor Iwao Teramoto

Iwao Teramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4675074
    Abstract: The invention provides a chemical etching method for a semiconductor device, which comprises a step of forming a first layer of Ga.sub.1-x Al.sub.x As (0.ltoreq.x<1) having a surface (100), a step of forming on the first layer a second layer of Ga.sub.1-y Al.sub.y As (0.ltoreq.y<1) having a surface (100), and a step of chemically etching the layers from a level above the second layer and along the direction of <011>. The slope angle of etch face of the second layer depends on the mol fraction y of the second layer, and the slope angle of etch face of the first layer depends on the mol fraction y of the second layer and the mol fraction x of the first layer. These facts are best utilized in the invention so that the etch profile of the first layer may have a desired slope angle.
    Type: Grant
    Filed: July 31, 1985
    Date of Patent: June 23, 1987
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaru Wada, Hirokazu Shimizu, Takao Shibutani, Kunio Itoh, Ken Hamada, Iwao Teramoto
  • Patent number: 4651322
    Abstract: In a laser of such type that the distribution of the effective refractive index varies in a direction which is along the face of its active layer and perpendicular to the direction of the laser light transmission, thereby defining the active region to be between a pair of refractive index changing zones, the refractive indexes of a pair of end surfaces of a laser resonator (i.e. the active region) is made smaller than the intrinsic refractive indexes of the cleavage face of the active layer.
    Type: Grant
    Filed: July 10, 1985
    Date of Patent: March 17, 1987
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hirokazu Shimizu, Kunio Itoh, Takashi Sugino, Masaru Wada, Iwao Teramoto, Kazuo Fujimoto
  • Patent number: 4432092
    Abstract: A very narrow current injection region (16") is made by means of terrace-shaping of the surface of the current limiting layer (13) forming a step thereon, the current limiting layer being on the epitaxially grown double hetero structure layers (10, 11 and 12) including the active layer (11). By so terrace-shaping, when Zn as a p-type impurity to form the current injection region (16) is diffused from the surface of the current limiting layer (13), the diffused region is formed to have a deeper part (16") and a shallower part (16'), and the deeper part (16") can be made very narrow by selecting the position of the stripe-shaped diffused region with respect to the step (14).
    Type: Grant
    Filed: June 4, 1981
    Date of Patent: February 14, 1984
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Iwao Teramoto, Takashi Sugino, Kunio Itoh
  • Patent number: 4351099
    Abstract: A novel self-align type method of making an FET with a very short gate length and a good high frequency characteristic, and a low noise characteristic, the method comprising the steps of:forming on a silicon epitaxial layer (13) of n-type conductivity a doped oxide film (14) containing boron as an impurity to give p-type conductivity,forming a mask (15a, 16a) containing Si.sub.3 N.sub.
    Type: Grant
    Filed: May 12, 1980
    Date of Patent: September 28, 1982
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiromitsu Takagi, Shotaro Umebachi, Gota Kano, Iwao Teramoto
  • Patent number: 4194927
    Abstract: In the process of forming a thermal oxide film or heat treatment of an oxide film in making a semiconductor device comprising a compound semiconductor of arsenic, the semiconductor is handled in an atmosphere containing arsenic oxide vapor in order to prevent evaporation of the arsenic tri-oxide in the thermal oxidation film or the oxide film under heat treatment, thereby to form a thermal oxide film having good chemical stability and good electrical characteristics, or to improve the oxide film so as to have good chemical stability and good electrical characteristics.
    Type: Grant
    Filed: July 11, 1978
    Date of Patent: March 25, 1980
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiromitsu Takagi, Gota Kano, Iwao Teramoto
  • Patent number: 4053798
    Abstract: A negative resistance device formed by series-connection of a complementary pair of insulated gate type FETs (field effect transistors), the source of the FETs being connected to each other and the gates of each of the FETs being connected to the respective drain of the other FET at least one FET having a double layered gate insulation film under the gate electrode, thereby forming a non-volatile memory element. The negative resistance device acquires or loses negative resistance characteristics by responding to signals to the gates, thereby memorizing the signals and resulting in a highly efficient memory which requires little power in writing-in, erasing and memory-holding.
    Type: Grant
    Filed: February 13, 1976
    Date of Patent: October 11, 1977
    Assignee: Matsushita Electronics Corporation
    Inventors: Susumu Koike, Gota Kano, Iwao Teramoto
  • Patent number: 3937949
    Abstract: An improvement in optical remote-control apparatus which comprises a light-beam transmitter and a light-receiver, wherein the improvement is that a light-scattering (i.e., light-diffusing) plate having a suitable area is provided in front of the light-receiver, so that the aiming tolerance of the light-beam transmitter becomes broader, enabling easy remote-control.
    Type: Grant
    Filed: May 30, 1973
    Date of Patent: February 10, 1976
    Assignee: Matsushita Electronics Corporation
    Inventors: Kiyotsugu Ishikawa, Tetsuo Kobune, Hitoo Iwasa, Iwao Teramoto