Patents by Inventor Iwen Chao
Iwen Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9543019Abstract: Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.Type: GrantFiled: December 11, 2012Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo, Kristopher H. Gaewsky
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Patent number: 9524774Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.Type: GrantFiled: November 30, 2015Date of Patent: December 20, 2016Assignee: Intel CorporationInventors: Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo, Kristopher H. Gaewsky
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Patent number: 9418000Abstract: Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.Type: GrantFiled: December 22, 2014Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Shyam Sunder Raghunathan, Iwen Chao, Xin Guo, Pranav Kalavade, Krishna K. Parat, Feng Zhu
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Publication number: 20160180958Abstract: Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.Type: ApplicationFiled: December 22, 2014Publication date: June 23, 2016Applicant: Intel CorporationInventors: SHYAM SUNDER RAGHUNATHAN, IWEN CHAO, XIN GUO, PRANAV KALAVADE, KRISHNA K. PARAT, FENG ZHU
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Publication number: 20160155497Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.Type: ApplicationFiled: November 30, 2015Publication date: June 2, 2016Applicant: Intel CorporationInventors: Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo, Kristopher H. Gaewsky
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Patent number: 9236136Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.Type: GrantFiled: December 14, 2012Date of Patent: January 12, 2016Assignee: Intel CorporationInventors: Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo, Kristopher H. Gaewsky
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Publication number: 20140173174Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Inventors: Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo, Kristopher H. Gaewsky
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Publication number: 20140164872Abstract: Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.Type: ApplicationFiled: December 11, 2012Publication date: June 12, 2014Inventors: Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo, Kristopher H. Gaewsky
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Publication number: 20130339603Abstract: Techniques and mechanisms for determining a sequence of accessed to a memory array. In an embodiment, a memory array includes multi-level cells and single-level cells interleaved with one another, where bits of the multi-level cells and single-level cells are variously allocated to different logical pages. In another embodiment, requests to access the memory array are ordered according to a sequence of page rounds to avoid an access event which includes a type of successive accessing of adjacent multi-level cells.Type: ApplicationFiled: December 23, 2011Publication date: December 19, 2013Inventors: Feng Zhu, Pranav Kalavade, Iwen Chao
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Patent number: 8400831Abstract: A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module.Type: GrantFiled: November 29, 2010Date of Patent: March 19, 2013Assignee: Intel CorporationInventors: Hoon Cho, Kiran Pangal, Krishna K. Parat, Neal R. Mielke, Pranav Kalavade, Iwen Chao
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Publication number: 20120137048Abstract: A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module.Type: ApplicationFiled: November 29, 2010Publication date: May 31, 2012Inventors: Hoon Cho, Kiran Pangal, Krishna K. Parat, Neal R. Mielke, Pranav Kalavade, Iwen Chao
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Patent number: 7741155Abstract: Some embodiments of the present invention relate to a semiconducting device and method that include a substrate and a first die that is attached to the substrate. The first die includes active circuitry (e.g., a flash memory array or logic circuitry) on an upper surface of the first die. The semiconducting device further includes a spacer that covers the active circuitry on the upper surface of the first die and a second die that is stacked onto the spacer and the first die. The spacer extends from a first side of the first die to an opposing second side of the first die. The spacer also extends near a third side of the first die and an opposing fourth side of the first die such that the active circuitry is exposed near the third and fourth sides of the first die.Type: GrantFiled: April 22, 2008Date of Patent: June 22, 2010Assignee: Intel CorporationInventors: Scott R. Sahaida, Iwen Chao
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Patent number: 7482698Abstract: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the interposer. The semiconducting device further includes a contact that is attached to the first surface of the interposer at the first section and the second section. A second die is attached to a second surface of the interposer such that the second die is stacked onto the first die and is electrically coupled to the first die by the contact and conductive paths that are part of the interposer.Type: GrantFiled: September 22, 2006Date of Patent: January 27, 2009Assignee: Intel CorporationInventors: Iwen Chao, Steve R. Eskildsen
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Patent number: 7456048Abstract: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the interposer. The semiconducting device further includes a contact that is attached to the first surface of the interposer at the first section and the second section. A second die is attached to a second surface of the interposer such that the second die is stacked onto the first die and is electrically coupled to the first die by the contact and conductive paths that are part of the interposer.Type: GrantFiled: September 22, 2006Date of Patent: November 25, 2008Assignee: Intel CorporationInventors: Iwen Chao, Steve R. Eskildsen
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Publication number: 20080280395Abstract: Some embodiments of the present invention relate to a semiconducting device and method that include a substrate and a first die that is attached to the substrate. The first die includes active circuitry (e.g., a flash memory array or logic circuitry) on an upper surface of the first die. The semiconducting device further includes a spacer that covers the active circuitry on the upper surface of the first die and a second die that is stacked onto the spacer and the first die. The spacer extends from a first side of the first die to an opposing second side of the first die. The spacer also extends near a third side of the first die and an opposing fourth side of the first die such that the active circuitry is exposed near the third and fourth sides of the first die.Type: ApplicationFiled: April 22, 2008Publication date: November 13, 2008Inventors: Scott R. Sahaida, Iwen Chao
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Patent number: 7378725Abstract: Some embodiments of the present invention relate to a semiconducting device and method that include a substrate and a first die that is attached to the substrate. The first die includes active circuitry (e.g., a flash memory array or logic circuitry) on an upper surface of the first die. The semiconducting device further includes a spacer that covers the active circuitry on the upper surface of the first die and a second die that is stacked onto the spacer and the first die. The spacer extends from a first side of the first die to an opposing second side of the first die. The spacer also extends near a third side of the first die and an opposing fourth side of the first die such that the active circuitry is exposed near the third and fourth sides of the first die.Type: GrantFiled: March 31, 2004Date of Patent: May 27, 2008Assignee: Intel CorporationInventors: Scott R. Sahaida, Iwen Chao
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Publication number: 20070026569Abstract: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the interposer. The semiconducting device further includes a contact that is attached to the first surface of the interposer at the first section and the second section. A second die is attached to a second surface of the interposer such that the second die is stacked onto the first die and is electrically coupled to the first die by the contact and conductive paths that are part of the interposer.Type: ApplicationFiled: September 22, 2006Publication date: February 1, 2007Inventors: Iwen Chao, Steve Eskildsen
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Publication number: 20070023905Abstract: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the interposer. The semiconducting device further includes a contact that is attached to the first surface of the interposer at the first section and the second section. A second die is attached to a second surface of the interposer such that the second die is stacked onto the first die and is electrically coupled to the first die by the contact and conductive paths that are part of the interposer.Type: ApplicationFiled: September 22, 2006Publication date: February 1, 2007Inventors: Iwen Chao, Steve Eskildsen
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Patent number: 7145249Abstract: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the interposer. The semiconducting device further includes a contact that is attached to the first surface of the interposer at the first section and the second section. A second die is attached to a second surface of the interposer such that the second die is stacked onto the first die and is electrically coupled to the first die by the contact and conductive paths that are part of the interposer.Type: GrantFiled: March 29, 2004Date of Patent: December 5, 2006Assignee: Intel CorporationInventors: Iwen Chao, Steve R. Eskildsen
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Publication number: 20050224943Abstract: Some embodiments of the present invention relate to a semiconducting device and method that include a substrate and a first die that is attached to the substrate. The first die includes active circuitry (e.g., a flash memory array or logic circuitry) on an upper surface of the first die. The semiconducting device further includes a spacer that covers the active circuitry on the upper surface of the first die and a second die that is stacked onto the spacer and the first die. The spacer extends from a first side of the first die to an opposing second side of the first die. The spacer also extends near a third side of the first die and an opposing fourth side of the first die such that the active circuitry is exposed near the third and fourth sides of the first die.Type: ApplicationFiled: March 31, 2004Publication date: October 13, 2005Inventors: Scott Sahaida, Iwen Chao