Abstract: A system for dissipating heat from a semiconductor board includes a first substrate including an opening formed therein, a second substrate attached to a surface of the first substrate, and a microchip positioned in the opening and bumped to the second substrate. The system further includes a heat sink directly adhered to the microchip. A method of manufacturing a heat dissipating semiconductor board includes forming an opening in a first substrate and positioning a microchip in the opening. The method further includes directly adhering the microchip to a heat sink, bonding the microchip to a second substrate and boding a surface of the first substrate to the second substrate.

Abstract: Disclosed is a mounting structure for mounting an IC on a substrate, and particularly useful in a Multi-Chip Module (MCM). The mounting structure intervenes between the IC and the MCM substrate, and promotes heat dissipation from the IC. The mounting structure is insulative, and preferably comprises a direct bond to copper (DBC) board. A heat spreading region to which the IC is affixed is formed on a surface of the mounting structure with bond pad areas are around the heat spreading region. The other side of the mounting structure is mounted to the substrate, which also has bond pads. Bond pads on the IC are connected to the bond pad areas on the mounting structure, and the bond pad areas on the mounting structure are further coupled to the bond pads on the substrate. Each of these connections is preferably made by wirebonding. Thermal vias can be used in the mounting structure and/or in the substrate to further promote heat dissipation.

Abstract: Disclosed is a mounting structure for mounting an IC on a substrate, and particularly useful in a Multi-Chip Module (MCM). The mounting structure intervenes between the IC and the MCM substrate, and promotes heat dissipation from the IC. The mounting structure is insulative, and preferably comprises a direct bond to copper (DBC) board. A heat spreading region to which the IC is affixed is formed on a surface of the mounting structure with bond pad areas are around the heat spreading region. The other side of the mounting structure is mounted to the substrate, which also has bond pads. Bond pads on the IC are connected to the bond pad areas on the mounting structure, and the bond pad areas on the mounting structure are further coupled to the bond pads on the substrate. Each of these connections is preferably made by wirebonding. Thermal vias can be used in the mounting structure and/or in the substrate to further promote heat dissipation.

Abstract: An oscillator package with an improved crystal mount. The oscillator package has substrate with a top cavity and a bottom cavity. Vias extend through the substrate between the top and bottom cavities. A semiconductor die is located in the bottom cavity and is covered by a sealant. A crystal is located in the top cavity. The crystal is mounted in the top cavity using a thermosonically deposited gold bump. The gold bump is attached between an electrode pad and a contact pad. The gold bump provides an electrical connection between the crystal and the substrate and supports the crystal. A cover and seal ring are attached to substrate to hermetically seal the top cavity.

Abstract: A method and apparatus are provided for reducing a startup interval of a temperature controlled crystal oscillator chip. The method includes the steps of connecting an operating circuit of the temperature controlled crystal oscillator chip into a first configuration to reduce the startup interval following application of power and reconnecting the operating circuit into a second configuration after a predetermined time period.

Abstract: A method and apparatus are provided for constructing a temperature controlled crystal oscillator chip. The method includes the steps of disposing a connection pad on a surface of the chip, providing a first circuit within the chip for control of a first chip function through a first interconnection with the connection pad and providing a second circuit within the chip for control of a second chip function, unrelated to the first chip function, through a second interconnection with the connection pad.

Abstract: A method and apparatus are provided for exchanging data with a temperature controlled crystal oscillator chip. The method includes the steps of receiving data within the temperature controlled crystal oscillator chip through a first bonding pad of the chip during a first time interval and transmitting data from the temperature controlled crystal oscillator chip through the first bonding pad of the chip during a second time interval.

Abstract: A method and apparatus are provided for reducing a startup interval of a temperature controlled crystal oscillator chip. The method includes the steps of connecting an operating circuit of the temperature controlled crystal oscillator chip into a first configuration to reduce the startup interval following application of power and reconnecting the operating circuit into a second configuration after a predetermined time period.

Abstract: A method and apparatus are provided for constructing a temperature controlled crystal oscillator chip. The method includes the steps of disposing a connection pad on a surface of the chip, providing a first circuit within the chip for control of a first chip function through a first interconnection with the connection pad and providing a second circuit within the chip for control of a second chip function, unrelated to the first chip function, through a second interconnection with the connection pad.

Abstract: A frequency synthesizer module with temperature compensation of a crystal oscillator circuit frequency controlled by a varactor. A module memory contains information characterizing a temperature dependency of a crystal which is applied to the varactor to temperature compensate the crystal in response to a temperature sensor signal. The module includes at least one locked loop circuit including a loop filter, at least one associated frequency divider, and a switchable dual band voltage controlled oscillator. The crystal oscillator is coupled to the at least one locked loop circuit and the frequency of the crystal is controlled by the memory via the varactor such that a temperature compensated output frequency is provided by the module.

Abstract: A method for etching (200) photolithographically produced quartz crystal blanks for singulation. First, a quartz wafer is plated on both sides with metal and subsequently coated on both sides with photoresist (202). Second, the photoresist is patterned and developed and the metal layers etched to define the periphery of a quartz blank with a narrow quartz channel exposed between the blank to be singulated and the parent quartz wafer (204). Third, the quartz channel is preferentially etched partially into the wafer along parallel atomic planes to provide a mechanically weak junction between the quartz wafer and the blank to be singulated, while the periphery around the remainder of the quartz blank is etched completely through the parent quartz wafer (206). Fourth, the photoresist layers are stripped from the quartz wafer (208). Finally, the quartz blank is cleaved substantially along the bottom of the quartz channel to singulate the crystal blank from the wafer (210).

Abstract: A piezoelectric resonator (10) with an attenuated spurious response. The resonator (10) includes a piezoelectric crystal plate (12) having opposite surfaces (14, 16), an electrode (18, 24) positioned and overlying relationship on each of the opposite surfaces (14, 16), the electrodes (18, 24) being substantially coextensive and opposite, and providing a primary frequency mode of operation and spurious modes upon suitable energization, and a number of mass loading structures (34) on at least one of the surfaces (14, 16) substantially surrounding at least one of the electrodes (18, 24).

Abstract: A method of compliantly mounting piezoelectric device with a substrate. First, outer portions of a piezoelectric element are selectively metallized. Next, one layer of aluminum is selectively dispensed on the piezoelectric element. Third, an uncured conductive compliant material is placed and aligned on a substrate. Fourth, the piezoelectric element is placed and aligned on the conductive compliant material, such that upon curing the conductive compliant material forms a compliant mount connecting the outer metallized portions of the piezoelectric element with the substrate.