Patents by Inventor Iyappan Subramanian

Iyappan Subramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiple-queue integer coalescing mapping algorithm with shared based time
    Patent number: 10102164
    Abstract: A mapping technique sets coalescing latency values for computing systems that use multiple data queues having a shared base timer. A computing system having at least one receive queue and at least one transmit queue receives user-provided coalescing latency values for the respective queues, and converts these user-provided latencies to coalescing latency hardware register values as well as a base timer register value for the shared base timer. The hardware register values for the coalescing latencies together with the shared base timer register value determine the coalescing latencies for the respective queues. This mapping technique allows a user to conveniently set coalescing latencies for multi-queue processing systems while shielding the user settings from hardware complexity.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 16, 2018
    Assignee: Ampere Computing LLC
    Inventors: Shushan Wen, Keyur Chudgar, Iyappan Subramanian
  • MULTIPLE-QUEUE INTEGER COALESCING MAPPING ALGORITHM WITH SHARED BASED TIME
    Publication number: 20180225240
    Abstract: A mapping technique sets coalescing latency values for computing systems that use multiple data queues having a shared base timer. A computing system having at least one receive queue and at least one transmit queue receives user-provided coalescing latency values for the respective queues, and converts these user-provided latencies to coalescing latency hardware register values as well as a base timer register value for the shared base timer. The hardware register values for the coalescing latencies together with the shared base timer register value determine the coalescing latencies for the respective queues. This mapping technique allows a user to conveniently set coalescing latencies for multi-queue processing systems while shielding the user settings from hardware complexity.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 9, 2018
    Inventors: Shushan Wen, Keyur Chudgar, Iyappan Subramanian
  • Multiple-queue integer coalescing mapping algorithm with shared based time
    Patent number: 9965419
    Abstract: A mapping technique sets coalescing latency values for computing systems that use multiple data queues having a shared base timer. A computing system having at least one receive queue and at least one transmit queue receives user-provided coalescing latency values for the respective queues, and converts these user-provided latencies to coalescing latency hardware register values as well as a base timer register value for the shared base timer. The hardware register values for the coalescing latencies together with the shared base timer register value determine the coalescing latencies for the respective queues. This mapping technique allows a user to conveniently set coalescing latencies for multi-queue processing systems while shielding the user settings from hardware complexity.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: May 8, 2018
    Assignee: Ampere Computing LLC
    Inventors: Shushan Wen, Keyur Chudgar, Iyappan Subramanian