Abstract: Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

Abstract: Integrated circuit structures having fin isolation regions continuous with gate cut plugs are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires or the fin and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure. A dielectric gate cut plug is in the gate cut. The dielectric gate cut plug is continuous with the dielectric structure.

Abstract: Integrated circuit structures having stress-inducing fin trim isolation regions bound by gate cuts are described. In an example, an integrated circuit structure includes an integrated circuit structure including a vertical stack of horizontal nanowires or a fin over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. The dielectric structure induces a stress on the vertical stack of horizontal nanowires or the fin. A dielectric gate cut plug is in contact with the gate structure and the dielectric structure, and is continuous from the gate structure to the dielectric structure.

Abstract: Integrated circuit structures having fin isolation regions continuous with gate cut plugs are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires or the fin and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure. A dielectric gate cut plug is in the gate cut. The dielectric gate cut plug is continuous with the dielectric structure.

Abstract: Integrated circuit structures having backside contact extensions are described. In an example, a structure includes a first and second pluralities of horizontally stacked nanowires or fins. First and second gate stacks are over the first and second pluralities of horizontally stacked nanowires or fins. An epitaxial source or drain structure is between the first and second pluralities of horizontally stacked nanowires or fin. A dielectric structure is over the first gate stack, over the second gate stack, and over the epitaxial source or drain structure, the dielectric structure having an opening over the epitaxial source or drain. A conductive structure is in the opening in the dielectric structure and on the epitaxial source or drain structure, the conductive structure having a top surface below a top of the opening. A conductive extension is on the conductive structure, the conductive extension in and protruding above the opening in the dielectric structure.

Abstract: Apparatus and methods are disclosed. An example lithography apparatus includes an ultraviolet (UV) source to expose a photoresist layer to UV light; and an extreme ultraviolet (EUV) source coupled to the UV source, the EUV source to expose the photoresist layer to EUV light to via a photomask, a combination of the UV light and the EUV light provide a pattern on the photoresist layer when a developer solution is applied to the photoresist layer.