Abstract: The invention provides a method of manufacturing a semiconductor device having a MOS transistor, a resistor element, etc on one semiconductor substrate, in which the number of masks and the number of manufacturing steps are decreased. In an NMOS formation region, a channel stopper layer is formed in a P type well by a first ion implantation process. Then a punch-through prevention layer is formed in the P type well by a second ion implantation process. On the other hand, in a first high resistor element formation region and a second high resistor element formation region, utilizing the first and second ion implantation processes, a resistor layer is formed in an N type well.

Abstract: The invention provides a method of manufacturing a semiconductor device having a MOS transistor, a resistor element, etc on one semiconductor substrate, in which the number of masks and the number of manufacturing steps are decreased. In an NMOS formation region, a channel stopper layer is formed in a P type well by a first ion implantation process. Then a punch-through prevention layer is formed in the P type well by a second ion implantation process. On the other hand, in a first high resistor element formation region and a second high resistor element formation region, utilizing the first and second ion implantation processes, a resistor layer is formed in an N type well.

Abstract: The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiO2 film covering edges of trench isolation films adjacent to a capacitor formation region, and the SiO2 film is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiO2 film remaining in this etching and a SiO2 film to be formed thereafter form a capacitor insulation film.

Abstract: A memory transistor and a high breakdown voltage MOS transistor are easily formed on the same semiconductor substrate without changing the operational characteristics of the memory transistor. The process of forming the tunnel insulation film of the memory transistor and the process of forming the gate insulation film of the MOS transistor are performed separately. Concretely, an insulation film to be a part of the tunnel insulation film and a silicon nitride film are formed on the whole surface, and then the silicon nitride film in a MOS transistor formation region is selectively removed using a photoresist layer. Then, the MOS transistor formation region is selectively oxidized using the remaining silicon nitride film as an anti-oxidation mask to form the gate insulation film of the MOS transistor having a selected thickness.

Abstract: This invention relates to a technology to form a polysilicon resistor having a high resistance in a semiconductor device using a silicide process.

Abstract: The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiO2 film covering edges of trench isolation films adjacent to a capacitor formation region, and the SiO2 film is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiO2 film remaining in this etching and a SiO2 film to be formed thereafter form a capacitor insulation film.

Abstract: A non-volatile memory cell and a high voltage MOS transistor on the same semiconductor chip without changing the characteristic of the non-volatile memory cell. A gate insulating film of a MOS transistor is formed using the steps of forming an oxide film 12 formed on a floating gate 14 of a split-gate type non-volatile memory cell and of forming a tunneling insulating film 16 formed on the floating gate 14 and the oxide film 12. The gate insulating film 13 of the MOS transistor is formed by a stacked layer of the oxide film 12 and tunneling insulating film 16. Thus, the quantity of heat treatment in the entire production process undergoes no change, and the optimized characteristic of the non-volatile memory undergoes no change.

Abstract: A non-volatile memory cell and a high voltage MOS transistor on the same semiconductor chip without changing the characteristic of the non-volatile memory cell. A gate insulating film of a MOS transistor is formed using the steps of forming an oxide film 12 formed on a floating gate 14 of a split-gate type non-volatile memory cell and of forming a tunneling insulating film 16 formed on the floating gate 14 and the oxide film 12. The gate insulating film 13 of the MOS transistor is formed by a stacked layer of the oxide film 12 and tunneling insulating film 16. Thus, the quantity of heat treatment in the entire production process undergoes no change, and the optimized characteristic of the non-volatile memory undergoes no change.