Patents by Inventor Izuru Yamada

Izuru Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8249637
    Abstract: An object of the present invention is to provide means for eliminating a transmission delay when transmitting emergency information for the sake of relief, security, or the like in a wireless device in conformity with the wireless LAN standard in which if radio waves transmitted from peripheral devices are detected, transmission has to be stopped. In a multimode wireless communication scheme having two or more communication schemes, priorities of the communication schemes are set. A high priority or low priority regarding to a message is described in a “message type” data field of a frame of a controlling channel output from the access point side to the terminal side. When the frame of the controlling channel is decrypted on the terminal side, the message type is confirmed, so that the type of a service channel used thereafter is confirmed and the channel is coupled.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: August 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Tsuboi, Izuru Yamada, Hiroki Ichikawa
  • Publication number: 20110021233
    Abstract: An object of the present invention is to provide means for eliminating a transmission delay when transmitting emergency information for the sake of relief, security, or the like in a wireless device in conformity with the wireless LAN standard in which if radio waves transmitted from peripheral devices are detected, transmission has to be stopped. In a multimode wireless communication scheme having two or more communication schemes, priorities of the communication schemes are set. A high priority or low priority regarding to a message is described in a “message type” data field of a frame of a controlling channel output from the access point side to the terminal side. When the frame of the controlling channel is decrypted on the terminal side, the message type is confirmed, so that the type of a service channel used thereafter is confirmed and the channel is coupled.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 27, 2011
    Inventors: Tsutomu TSUBOI, Izuru Yamada, Hiroki Ichikawa
  • Publication number: 20110006922
    Abstract: The present invention provides a method for detecting the current location of a bus at lower cost without using a wideband wireless communication device and displaying it on each bus stop. A center system of a center and each of bus stop systems are coupled to each other via Internet. A roadside wireless unit of the bus stop system contained in the bus stop periodically outputs a beacon containing a bus stop ID to a route bus system equipped on a route bus. The route bus system outputs an ID notification signal including a bus stop ID and a bus ID to the bus stop system. The center system of the center updates location information using the bus stop ID and the bus ID and transmits bus location update data to a suitable target. The bus stop system displays a bus location thereon using the transmitted bus location update data.
    Type: Application
    Filed: July 5, 2010
    Publication date: January 13, 2011
    Inventors: Tsutomu TSUBOI, Izuru YAMADA, Hitoshi HARADA
  • Patent number: 4687998
    Abstract: A pulse generating circuit is provided for generating a pulse having a time width synchronized with an input pulse and corresponding to a reference voltage. The circuit is particularly designed not to be affected by parasitic capacitance. A circuit for charging one electrode of an integrating circuit with a constant current is controlled by turning on or off a switch in response to the input pulse. The other electrode of the integrating capacitor is connected with a reference voltage source by driving a switch in response to a pulse having a pulse width which contains the time period of the input pulse and which is wider than the input pulse. A comparator is provided for comparing the potential at one electrode of the integrating capacitor and ground potential. A desired pulse is generated by a logic circuit which is receives both the output of the comparator and the input pulse.
    Type: Grant
    Filed: July 29, 1985
    Date of Patent: August 18, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Takatori, Toshiro Suzuki, Osamu Matsubara, Izuru Yamada
  • Patent number: 4707654
    Abstract: An integrated circuit is constructed in order that tests can be conducted on a plurality of circuits to determine which of the circuits is defective. In particular, the circuit is constructed to allow such testing with the use of fewer input and output pins for testing. To accomplish this, a first buffer gate circuit, a resistor, and a second buffer gate are connected in series in the order mentioned between the output terminal of a first circuit and the input terminal of a second circuit. An input and output terminal pin for testing is located at a junction point of the resistor and second buffer gate.
    Type: Grant
    Filed: September 6, 1985
    Date of Patent: November 17, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Toshiro Suzuki, Fumiaki Fujii, Izuru Yamada