Abstract: A modular cluster tool is disclosed. According to one embodiment, a system, comprises a wafer transfer station that includes a first vacuum chamber that stores a plurality of semiconductor wafers. The system also includes an equipment front end module interface, and two or more shuttle lock interfaces.

Abstract: A method and apparatus for semiconductor processing is disclosed. In one embodiment, a method of transporting a wafer within a cluster tool, comprises placing the wafer into a first segment of a vacuum enclosure, the vacuum enclosure being attached to a processing chamber and a factory interface. The wafer is transported to a second segment of the vacuum enclosure using a vertical transport mechanism, wherein the second segment is above or below the first segment.

Abstract: A modular cluster tool is disclosed. According to one embodiment, a system, comprises a wafer transfer station that includes a first vacuum chamber that stores a plurality of semiconductor wafers. The system also includes an equipment front end module interface, and two or more shuttle lock interfaces.

Abstract: A method and apparatus for semiconductor processing is disclosed. In one embodiment, a method of transporting a wafer within a cluster tool, comprises placing the wafer into a first segment of a vacuum enclosure, the vacuum enclosure being attached to a processing chamber and a factory interface. The wafer is transported to a second segment of the vacuum enclosure using a vertical transport mechanism, wherein the second segment is above or below the first segment.

Abstract: A method and apparatus for semiconductor processing is disclosed. In one embodiment, a method of transporting a wafer within a cluster tool, comprises placing the wafer into a first segment of a vacuum enclosure, the vacuum enclosure being attached to a processing chamber and a factory interface. The wafer is transported to a second segment of the vacuum enclosure using a vertical transport mechanism, wherein the second segment is above or below the first segment.

Abstract: A method and apparatus for semiconductor processing is disclosed. In one embodiment, a method of transporting a wafer within a cluster tool, comprises placing the wafer into a first segment of a vacuum enclosure, the vacuum enclosure being attached to a processing chamber and a factory interface. The wafer is transported to a second segment of the vacuum enclosure using a vertical transport mechanism, wherein the second segment is above or below the first segment.

Abstract: Tungsten disilicide (WSi.sub.x) films are deposited onto doped or undoped polysilicon by reducing WF.sub.6 with a mixture of dichlorosilane (SiH.sub.2 Cl.sub.2) and disilane (Si.sub.2 H.sub.6). The addition of disilane provides a mechanism for increasing the resistivity (silicon to tungsten ratio) of the film without adversely affecting the uniformity or deposition rate of the film. A high silicon to tungsten ratio prevents degradation of the silicide film and the underlaying polysilicon film during subsequent growth of an oxide (SiO.sub.2) dielectric. The excess silicon in the film also provides desirable etching and annealing characteristics.

Abstract: Apparatus for the nitridiation of a silicon-bearing substrate is disclosed. The apparatus includes a double walled reaction vessel having first and second concentric walls bounding a reaction volume. Temperature of the reaction volume is controlled by resistance heaters located outside the outermost of the two concentric tubes. Plasma electrodes are positioned about the reaction volume and between the two concentric tubes. The ambient between the two tubes is controlled to protect the electrodes from oxidation at the high temperatures to which they are exposed. An rf generator is coupled to the plasma electrodes and is controllable independently from the resistance heaters.

Abstract: A compact load lock and processing chamber is disclosed in which a moveable member forms a closure for both a load lock volume and an article processing volume. The moveable member is connected to fixed members by a flexible diaphragm which provides a non-sliding seal.

Abstract: The temperature of a wafer in a vacuum chamber is measured by way of a tube, containing a thermocouple, extending through a wall of the chamber. The tube is sealed at one end to an aperture in the wall of the system and sealed at the other end with removable sealant.

Abstract: A process is disclosed for depositing tungsten non-selectively on conductors and dielectrics without the use of an adhesive interlayer. The process comprises an argon pre-treatment followed by low power plasma deposition to nucleate the tungsten. A thick, adherent layer of tungsten is then deposited.

Abstract: A process is disclosed for reducing lateral encroachment and silicon consumption in LPCVD of tungsten. The process comprises a low temperature deposition of a thin layer of tungsten, followed by annealing in nitrogen at high temperature, follows by deposition of a thick layer of tungsten.

Abstract: A process for forming a bonding layer comprising amorphous silicon, titanium, chromium, or tungsten, between the silicide and the N+ polysilicon layer is disclosed. The bonding layer is preferably less than 50 nm. thick. After the bonding layer is deposited, a silicide layer is deposited and the wafer is then sintered at 900.degree.-1000.degree. C. for ten minutes or less.

Abstract: Chemical vapor deposition on a semiconductor wafer is obtained in a plasma reactor having a plurality of lamps for radiantly heating the wafer. Calibrated temperature sensing means remote from the wafer is used to control the heating of the wafer. Gases are supplied by way of a plurality of tubes extending radially inwardly from the sides of the chamber. A baffle is provided to form an antechamber which aids in the uniformity of the deposition. The plasma is ignited for less than the whole deposition cycle for deposition of tungsten disilicide.

Abstract: Chemical vapor deposition on a semiconductor wafer is obtained in a plasma reactor having a plurality of lamps for radiantly heating the wafer. Calibrated temperature sensing means remote from the wafer is used to control the heating of the wafer. Gases are supplied by way of a plurality of tubes extending radially inwardly from the sides of the chamber. A baffle is provided to form an antechamber which aids in the uniformity of the deposition. The plasma is ignited for less than the whole deposition cycle for deposition of tungsten disilicide.

Abstract: Chemical vapor deposition on a semiconductor wafer is obtained in a plasma reactor having a plurality of lamps for radiantly heating the wafer. Calibrated temperature sensing means remote from the wafer is used to control the heating of the wafer. Gases are supplied by way of a plurality of tubes extending radially inwardly from the sides of the chamber. A baffle is provided to form an antechamber which aids in the uniformity of the deposition. The plasma is ignited for less than the whole deposition cycle for deposition of tungsten disilicide.

Abstract: Chemical vapor deposition on a semiconductor wafer is obtained in a plasma reactor having a plurality of lamps for radiantly heating the wafer. Calibrated temperature sensing means remote from the wafer is used to control the heating of the wafer. Gases are supplied by way of a plurality of tubes extending radially inwardly from the sides of the chamber. A baffle is provided to form an antechamber which aids in the uniformity of the deposition. The plasma is ignited for less than the whole deposition cycle for deposition of tungsten disilicide.

Abstract: An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.

Abstract: An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.