Abstract: A seedable pseudo-random number generator. A linear feedback shift register (LFSR) arrangement is used to generate a first pseudo-random number, and a cellular automata is used to generate a second pseudo-random number. The bits of the LFSR arrangement are XORed with bits of the cellular automata to generate the output pseudo-random number.

Abstract: The present invention is a counter that takes advantage of the speed and implementation of the LFSR counter by utilizing separate digit counters, each digit counter having a period that is a relative prime to the other digit counter periods. The total period will be the product of all the digit counter periods. Since all digits count independently, there is no carry structure between the digits and hence no delay incurred by carry chains. The pseudorandom number counting sequence for each digit still occurs but is ameliorated by the fact that the digital periods are small and can readily be converted to decimal equivalents by table-lookup and residue lookup.

Abstract: A fitness function circuit for computing a fitness value for a trial solution to a combinatorial problem accelerates the execution speed of a genetic algorithm machine by evaluating trial solutions at the rate of one evaluated solution per clock cycle. The circuit uses repeated tables of data which describe costs associated with each portion of each trial solution to find the total cost associated with each solution. By increasing memory used and repeating the data tables rather than accessing one table multiple times, and by adding each portion of each trial solution substantially simultaneously, the speed of one evaluated solution per one clock cycle is achieved.

Abstract: The present invention provides a method and apparatus to check the arithmetic increment function through prediction of the change in the bit-level parity of the result by means of a series of identical cells connected in a linear array. The array predicts the change in parity produced by the arithmetic increment function which allows the increment function to be checked in an efficient manner. The advantages of the present invention are that the parity check design saves hardware cost over prior schemes that require duplication of incrementers and comparison of the results and schemes that require generation of parity after incrementing, and that the iterative, identical cell implementation of the parity predictor is well-suited for current VLSI and future digital logic circuits as they progress towards molecular, self-assembling components.

Abstract: A system and a method to generate cellular automata based random number generators (CA-based RNGs) are presented A CA-based RNG is where an output of each cell of the CA at time t is dependent on inputs from any cells of the CA (including perhaps itself) at time t?1. The connections (or inputs) are selected to produce high entropy such that the RNG passes a standard suite of random number of tests, such as the DIEHARD suite. The RNGs may be implemented with field programmable gate arrays.

Abstract: The present invention provides a method and apparatus to significantly accelerate the searching process based on the Monte Carlo principle and the lattice model. Specifically, the energy status of a lattice-based protein conformation is evaluated by modeling the folding process through a pipelined digital circuit using a number of state machines. The pipelined digital circuit reduces the time required for the determination of the energy status of a particular conformation and, therefore, significantly accelerates the searching speed for the lowest energy status. The present invention also permits real-time tuning of problem parameters by the experimenter.

Abstract: A system and a method to reduce a search space to determine viable cellular automata based random number generators (CA-based RNGs) are presented. A CA-based RNG is where an output of each cell of the CA at time t is dependent on inputs from any cells of the CA (including perhaps itself) at time t?1. The connections (or inputs) are selected to produce high entropy such that the RNG passes a standard suite of random number of tests, such as the DIEHARD suite. As the number of inputs grow (corresponding to the neighborhood size), the number of truth tables grows dramatically. By reducing the search space of viable CA-based RNGs, high quality random number generators with higher neighborhood sizes may be found.

Abstract: A ones counter that accepts a binary input word of ones and zeros and provides a binary output word indicative of the number of ones within the input word. A two-dimensional array is built with a plurality of like cells connected in a regular manner with the first row of the array determining the least significant bit of the output word and each subsequent row determining the output word's next most significant bit. The first row of the array contains approximately one-half the number of cells as bits in the input word with each subsequent row of the array containing approximately one-half the number of cells of the preceding row with the final row containing a single cell that determines the most significant bit of the binary output word. The ones-count output word is computed asynchronously without clocking circuits or data storage elements.

Abstract: A ones counter that accepts a binary input word of ones and zeros and provides a binary output word indicative of the number of ones within the input word. A two-dimensional array is built with a plurality of like cells connected in a regular manner with the first row of the array determining the least significant bit of the output word and each subsequent row determining the output word's next most significant bit. The first row of the array contains approximately one-half the number of cells as bits in the input word with each subsequent row of the array containing approximately one-half the number of cells of the preceding row with the final row containing a single cell that determines the most significant bit of the binary output word. The ones-count output word is computed asynchronously without clocking circuits or data storage elements.

Abstract: A method and apparatus is used select a multiplication constant for addressing a storage location with reduced processing requirements. The selection includes receiving a multiplication constant for use in an arithmetic operation to address a storage location, determining an upper limit multiplication constant compared with the received multiplication constant, counting the number of zero digits for each binary value contained in the range of binary values greater than the multiplication constant value and less than or equal to the upper limit multiplication constant and selecting the binary value from the range having the greatest number of zero digits as the modified multiplication constant.

Abstract: A method and apparatus is used to initialize a population memory of electronic chromosomes for use in genetic algorithm (GA) analysis. Initializing the population memory includes providing an initial state into a first parent chromosome and a second parent chromosome, entering a current state of a first parent chromosome and a second parent chromosome into a cellular automata, selecting a neighbor state of the second parent chromosome for entry into the cellular automata, and generating a random number sequence using the cellular automata for use in the population memory.

Abstract: A method and apparatus is used to organize aspects of electronic chromosomes for use in genetic algorithm (GA) analysis. The organization operations include receiving one or more elements for composing into an electronic chromosome analyzed using a genetic algorithm, ordering each of the one or more elements into an element sequence as determined by a fitness function, selecting a binary number sequence having a single-bit difference between each pair of adjacent binary numbers, and sequentially associating each of the one or more elements in the element sequence with a binary number in accordance with the binary number sequence.

Abstract: A method and apparatus reduces storage requirements for identifying a sequence of elements in a compound. The storage reduction receives a set of monoisotopic masses designed to address entries from two or more mass spectroscopy data sets according to a fitness function, analyzes the fitness function configured to facilitate identification of a sequence of elements in the compound, determines a minimum address range for addressing entries in each of the two or more mass spectroscopy data sets according to sequence of elements and fitness function analysis and reduces the size of at least one of the two or more mass spectroscopy data sets to selected mass data values according to the minimum address range.

Abstract: The present invention provides a method and apparatus to check the arithmetic increment function through prediction of the change in the bit-level parity of the result by means of a series of identical cells connected in a linear array. The array predicts the change in parity produced by the arithmetic increment function which allows the increment function to be checked in an efficient manner. The advantages of the present invention are that the parity check design saves hardware cost over prior schemes that require duplication of incrementers and comparison of the results and schemes that require generation of parity after incrementing, and that the iterative, identical cell implementation of the parity predictor is well-suited for current VLSI and future digital logic circuits as they progress towards molecular, self-assembling components.

Abstract: A seedable pseudo-random number generator. A linear feedback shift register (LFSR) arrangement is used to generate a first pseudo-random number, and a cellular automata is used to generate a second pseudo-random number. The bits of the LFSR arrangement are XORed with bits of the cellular automata to generate the output pseudo-random number.

Abstract: A cellular array for generating a stream of random numbers in a Gaussian distribution from a stream of random numbers in a uniform distribution includes identical, repeating cells that receive one bit as input, store the bit, add the bit to a previously stored bit, and produce one sum bit as output. The cellular array is a hardware-based, flexible array that is advantageous to integrated circuit implementation, in that all of the connections are local, and also rapidly producing a stream of random numbers in a Gaussian distribution.

Abstract: A method and apparatus for searching a parent code sequence for a target code sequence. In various embodiments, a first circuit arrangement selects and stores subsets of codes of the parent code sequence. A matching circuit determines in parallel matches between the subset of codes and the target code sequence, and provides a programmed binary value for each match. The binary values provided by the matching circuit are summed in a pipelined fashion.

Abstract: A genetic algorithm machine with user-controlled parameters that is non-problem specific. A user interface directly manipulates several input parameters, the number of crossovers per run, the probability that any bit will be a cutpoint, and the probability that any bit will be mutated, that constrain the genetic algorithm machine's solving capabilities, allowing the user to control whether and how efficiently the genetic algorithm evolves a best solution.

Abstract: A system and a method to reduce a search space to determine viable cellular automata based random number generators (CA-based RNGs) are presented. A CA-based RNG is where an output of each cell of the CA at time t is dependent on inputs from any cells of the CA (including perhaps itself) at time t−1. The connections (or inputs) are selected to produce high entropy such that the RNG passes a standard suite of random number of tests, such as the DIEHARD suite. As the number of inputs grow (corresponding to the neighborhood size), the number of truth tables grows dramatically. By reducing the search space of viable CA-based RNGs, high quality random number generators with higher neighborhood sizes may be found.

Abstract: A fitness function circuit for computing a fitness value for a trial solution to a combinatorial problem accelerates the execution speed of a genetic algorithm machine by evaluating trial solutions at the rate of one evaluated solution per clock cycle. The circuit uses repeated tables of data which describe costs associated with each portion of each trial solution to find the total cost associated with each solution. By increasing memory used and repeating the data tables rather than accessing one table multiple times, and by adding each portion of each trial solution substantially simultaneously, the speed of one evaluated solution per one clock cycle is achieved.