Patents by Inventor J. Bentley

J. Bentley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347745
    Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure above a substrate, performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during the epi deposition process and, after performing the epi deposition process, forming a gate structure around a portion of the vertically oriented channel semiconductor structure.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Puneet Harischandra Suvarna, Steven J. Bentley, Daniel Chanemougame
  • Patent number: 10321954
    Abstract: A tissue interface module has an applicator chamber on a proximal side of the tissue interface module and a tissue acquisition chamber on a distal side of the tissue interface module. The applicator chamber may include: an opening adapted to receive the applicator; an attachment mechanism positioned in the applicator chamber and adapted to attach the tissue interface module to the applicator; a sealing member positioned at a proximal side of the applicator chamber; and a vacuum interface positioned at a proximal side of the applicator chamber and adapted to receive a vacuum inlet positioned on a distal end of the applicator. The invention also includes corresponding methods.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: June 18, 2019
    Assignee: MIRADRY, INC.
    Inventors: Yoav Ben-Haim, Peter J. Bentley, Donghoon Chun, Daniel E. Francis, Jessi E. Johnson, Kevin Shan, Ted Y. Su, Steven W. Kim
  • Patent number: 10236292
    Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Puneet H. Suvarna, Hiroaki Niimi, Steven J. Bentley, Ali Razavieh
  • Patent number: 10192867
    Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Puneet H. Suvarna, Hiroaki Niimi, Steven J. Bentley, Ali Razavieh
  • Patent number: 10170616
    Abstract: One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Steven J. Bentley, Jody A. Fronheiser
  • Publication number: 20180083136
    Abstract: One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 22, 2018
    Inventors: Ruilong Xie, Steven J. Bentley, Jody A. Fronheiser
  • Publication number: 20180083121
    Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure above a substrate, performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during the epi deposition process and, after performing the epi deposition process, forming a gate structure around a portion of the vertically oriented channel semiconductor structure.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 22, 2018
    Inventors: Puneet Harischandra Suvarna, Steven J. Bentley, Daniel Chanemougame
  • Patent number: 9799751
    Abstract: One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: October 24, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John H. Zhang, Steven J. Bentley, Kwan-Yong Lim
  • Publication number: 20170301776
    Abstract: One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.
    Type: Application
    Filed: April 19, 2016
    Publication date: October 19, 2017
    Inventors: John H. Zhang, Steven J. Bentley, Kwan-Yong Lim
  • Patent number: 9640636
    Abstract: One illustrative method disclosed herein includes, among other things, forming an initial vertically oriented channel semiconductor structure having a first height above a substrate, forming a sacrificial spacer structure adjacent the initial vertically oriented channel semiconductor structure and, with the sacrificial spacer in position, performing at least one process operation to define a self-aligned bottom source/drain region for the device that is self-aligned with respect to the sacrificial spacer structure, forming an isolation region in the trench and forming a bottom source/drain electrode above the isolation region. The method also includes removing the sacrificial spacer structure and forming a bottom spacer material around the vertically oriented channel semiconductor structure above the bottom source/drain electrode.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: May 2, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven J. Bentley, John H. Zhang, Kwan-Yong Lim, Hiroaki Niimi
  • Patent number: 9530863
    Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure, forming a layer of a bottom spacer material around the vertically oriented channel semiconductor structure and forming a sacrificial material layer above the layer of a bottom spacer material. In this example, the method further includes forming a sidewall spacer adjacent the vertically oriented channel semiconductor structure and above an upper surface of the sacrificial material layer, removing the sacrificial material layer so as to define a replacement gate cavity between a bottom surface of the sidewall spacer and the layer of a bottom spacer material, and forming a replacement gate structure in the replacement gate cavity.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: December 27, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John H. Zhang, Carl Radens, Steven J. Bentley, Brian A. Cohen, Kwan-Yong Lim
  • Patent number: 9530864
    Abstract: Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: December 27, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven J. Bentley, Michael J. Hargrove, Chia-Yu Chen, Ryan O. Jung, Sivanandha K. Kanakasabapathy, Tenko Yamashita
  • Patent number: 9530866
    Abstract: Forming a first sidewall spacer adjacent a vertically oriented channel semiconductor structure (“VCS structure’) and adjacent a cap layer, performing at least one planarization process so as to planarize an insulating material and expose an upper surface of the cap layer and an upper surface of the first spacer and removing a portion of the first spacer and an entirety of the cap layer so as to thereby expose an upper surface of the VCS structure and define a spacer/contact cavity above the VCS structure and the first spacer. The method also includes forming a second spacer in the spacer/contact cavity, forming a top source/drain region in the VCS structure and forming a top source/drain contact within the spacer/contact cavity that is conductively coupled to the top source/drain region, wherein the conductive contact physically contacts the second spacer in the spacer/contact cavity.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: December 27, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John H. Zhang, Carl Radens, Steven J. Bentley, Brian A. Cohen, Kwan-Yong Lim
  • Publication number: 20160254361
    Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.
    Type: Application
    Filed: May 13, 2016
    Publication date: September 1, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Steven J. Bentley, Ajey Poovannummoottil Jacob, Chia-Yu Chen, Tenko Yamashita
  • Publication number: 20160213426
    Abstract: A tissue interface module has an applicator chamber on a proximal side of the tissue interface module and a tissue acquisition chamber on a distal side of the tissue interface module. The applicator chamber may include: an opening adapted to receive the applicator; an attachment mechanism positioned in the applicator chamber and adapted to attach the tissue interface module to the applicator; a sealing member positioned at a proximal side of the applicator chamber; and a vacuum interface positioned at a proximal side of the applicator chamber and adapted to receive a vacuum inlet positioned on a distal end of the applicator. The invention also includes corresponding methods.
    Type: Application
    Filed: April 4, 2016
    Publication date: July 28, 2016
    Inventors: Yoav BEN-HAIM, Peter J. BENTLEY, Donghoon CHUN, Daniel E. FRANCIS, Jessi E. JOHNSON, Kevin SHAN, Ted Y. SU, Steven W. KIM
  • Patent number: 9368591
    Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: June 14, 2016
    Assignee: GlobalFoundries Inc.
    Inventors: Steven J. Bentley, Ajey Poovannummoottil Jacob, Chia-Yu Chen, Tenko Yamashita
  • Patent number: 9314301
    Abstract: An tissue interface module has an applicator chamber on a proximal side of the tissue interface module and a tissue acquisition chamber on a distal side of the tissue interface module. The applicator chamber may include: an opening adapted to receive the applicator; an attachment mechanism positioned in the applicator chamber and adapted to attach the tissue interface module to the applicator; a sealing member positioned at a proximal side of the applicator chamber; and a vacuum interface positioned at a proximal side of the applicator chamber and adapted to receive a vacuum inlet positioned on a distal end of the applicator. The invention also includes corresponding methods.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: April 19, 2016
    Assignee: Miramar Labs, Inc.
    Inventors: Yoav Ben-Haim, Peter J. Bentley, Dong Hoon Chun, Daniel Francis, Jessi E. Johnson, Kevin Shan, Ted Su, Steven Kim
  • Publication number: 20160020335
    Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.
    Type: Application
    Filed: July 18, 2014
    Publication date: January 21, 2016
    Inventors: Steven J. Bentley, Ajey Poovannummoottil Jacob, Chia-Yu Chen, Tenko Yamashita
  • Publication number: 20150380514
    Abstract: Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.
    Type: Application
    Filed: June 25, 2014
    Publication date: December 31, 2015
    Inventors: Steven J. Bentley, Michael J. Hargrove, Chia-Yu Chen, Ryan O. Jung, Sivanandha K. Kanakasabapathy, Tenko Yamashita
  • Patent number: 9183501
    Abstract: An information technology (IT) architecture upper merged ontology which includes an upper merged ontology that is a representation framework for combined knowledge sources that are used in business and information technology; an upper merged ontology knowledge base containing information derived from an analysis of business and technical services pertaining to the IT architecture application; a plurality of semantic web application programming interfaces (APIs) that allow access to the upper merged ontology as a semantic web; a reasoning and constraint language (RaCL) that is a scripting language having the capabilities of model creation, automated reasoning and search and query operations such that scripts developed in the reasoning and constraint language can execute using the semantic web APIs; and a computer processor for representing and performing execution tasks.
    Type: Grant
    Filed: May 11, 2013
    Date of Patent: November 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Andrew J. Bentley, Rhonda L. Childress, Christopher J. De Vaney, Steven O. Twist