Patents by Inventor J. Brennan

J. Brennan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230097097
    Abstract: Systems, apparatuses, and methods for preemptively reserving buffer space for primitives and positions in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with any number of geometry engines coupled to corresponding shader engines. Each geometry engine launches shader wavefronts to execute on a corresponding shader engine. The geometry engine preemptively reserves buffer space for each wavefront prior to the wavefront being launched on the shader engine. When the shader engine executes a wavefront, the shader engine exports primitive and position data to the reserved buffer space. Multiple scan converters will consume the primitive and position data, with each scan converter consuming primitive and position data based on the screen coverage of the scan converter. After consuming the primitive and position data, the scan converters mark the buffer space as freed so that the geometry engine can then allocate the freed buffer space to subsequent shader wavefronts.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 30, 2023
    Inventors: Todd Martin, Tad Robert Litwiller, Nishank Pathak, Randy Wayne Ramsey, Michael J. Mantor, Christopher J. Brennan, Mark M. Leather, Ryan James Cash
  • Patent number: 11614889
    Abstract: An operation combiner receives a series of commands with read addresses, a modification operation, and write addresses. In some cases, the commands have serial dependencies that limit the rate at which they can be processed. The operation combiner compares the addresses for compatibility, transforms the operations to break serial dependencies, and combines multiple source commands into a smaller number of aggregate commands that can be executed much faster than the source commands. Some embodiments of the operation combiner receive a first command including one or more first read addresses and a first write address. The operation combiner compares the first read addresses and the first write address to one or more second read addresses and a second write address of a second command stored in a buffer. The operation combiner selectively combines the first and second commands to form an aggregate command based on the comparison.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 28, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Christopher J. Brennan
  • Patent number: 11581913
    Abstract: Accordingly, there are disclosed herein active cables and methods that enable direct connection between different generations of network interface ports or ports supporting different standards. One illustrative embodiment is an active 1:N breakout cable that includes a unary end connector connected by electrical conductors to each of multiple split end connectors. The unary end connector is adapted to fit into a network interface port of a primary host device to provide output PAM4 electrical signals that convey a multi-lane outbound data stream to the primary host device and to accept input PAM4 electrical signals that convey multi-lane inbound data stream from the primary host device.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 14, 2023
    Assignee: CREDO TECHNOLOGY GROUP LTD
    Inventors: Yattung Lam, Baohua Chen, Yifei Dai, William J. Brennan
  • Publication number: 20220414939
    Abstract: A disclosed technique includes reading, from a compressed render target, a set of unique color values for a coarse pixel, wherein the coarse pixel includes multiple render target pixels; reading, from the compressed render target, pointers to the unique color values for the coarse pixel; and generating colors for the multiple render target pixels based on the unique color values and the pointers.
    Type: Application
    Filed: June 28, 2021
    Publication date: December 29, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Pazhani Pillai, Christopher J. Brennan
  • Publication number: 20220414950
    Abstract: A disclosed technique includes determining a plurality of per-pixel variable rate shading rates for a plurality of fragments; determining a coarse variable shading rate for a coarse variable rate shading area based on the plurality of per-pixel variable rate shading rates; and shading one or more fragments based on the plurality of fragments and based on the coarse variable shading rate.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 29, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Christopher J. Brennan
  • Patent number: 11488328
    Abstract: Systems, apparatuses, and methods for implementing automatic data format detection techniques are disclosed. A graphics engine receives data of indeterminate format and the graphics engine predicts an organization of the data. As part of the prediction, the graphics engine predicts the pixel depth (i.e., bytes per pixel (BPP)) and format separately. The graphics engine folds the data along pixel and channel boundaries to help in determining the pixel depth and format. The graphics engine scores modes against each other to generate different predictions for different formats. Then, the graphics engine generates scores for the predictions to determine which mode has a highest correlation with the input data. Next, the graphics engine chooses the format which attains the best score among the scores that were generated for the different modes. Then, the graphics engine compresses the unknown data using the chosen format with the best score.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 1, 2022
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Chan, Nooruddin Ahmed, Christopher J. Brennan, Bernard T. K. Chan
  • Patent number: 11481967
    Abstract: Systems, apparatuses, and methods for executing a shader core instruction to invoke depth culling are disclosed. A shader core executes an instruction to invoke a culling function on a depth culling unit for one or more entities prior to completing a corresponding draw call. The shader core provides a mode and coordinates to the depth culling unit as a result of executing the instruction. The depth culling unit implements the culling function to access a live depth buffer to determine whether one or more primitives corresponding to the entities are occluded. The culling unit returns indication(s) to the shader core regarding the result(s) of processing the one or more primitives. For example, if the results indicate a primitive is occluded, the shader core cancels the draw call for the primitive.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: October 25, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthäus G. Chajdas, Christopher J. Brennan
  • Publication number: 20220318944
    Abstract: A graphics pipeline includes a first shader that generates first wave groups, a shader processor input (SPI) that launches the first wave groups for execution by shaders, and a scan converter that generates second waves for execution on the shaders based on results of processing the first wave groups the one or more shaders. The first wave groups are selectively throttled based on a comparison of in-flight first wave groups and second waves pending execution on the at least one second shader. A cache holds information that is written to the cache in response to the first wave groups finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first wave groups are selectively throttled by comparing how many first wave groups are in-flight and how many read requests to the cache are pending.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 6, 2022
    Inventors: Christopher J. BRENNAN, Nishank PATHAK
  • Patent number: 11455701
    Abstract: Computer-implemented functionality is described herein for assisting a user in interacting with an environment. In one implementation, the functionality operates by: determining that a particular user is within a prescribed proximity to an electronic sign, or will be in prescribed proximity to the electronic sign, based on sensor information provided by one or more sensors within the environment; determining an identity of the user; determining at least one destination of the user based at least on calendar information; providing directions to the destination(s), to provide unfiltered direction information; optionally filtering the unfiltered direction information with respect to restriction information (e.g., privacy information, security information, etc.), to produce filtered direction information; composing sign information based on the filtered direction information; and sending the sign information to the electronic sign for presentation by the sign.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 27, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Hubert Van Hoof, David M. Gray, Scott E. Seiber, David J. Brennan, John R. Sanders
  • Patent number: 11448673
    Abstract: A device having an impedance measurement circuit that allows for reduction of flicker noise can be implemented in a variety of applications. A carrier suppression technique can be implemented that substantially removes the carrier signal with removal of noise artifacts associated with the carrier signal from sidebands of the carrier signal. Carrier suppression in an AC impedance measurement circuit can be implemented by sensing a carrier signal of the measurement circuit at a transmit location of the measurement circuit and subtracting a weighted version of the carrier signal at a receive location of the measurement circuit. One or more compensation impedances can be used such that the sidebands of the carrier signal are received with the carrier signal suppressed with respect to the receive location.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: September 20, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Colin G. Lyden, Thomas J. Tansley, Oliver J. Brennan
  • Publication number: 20220220292
    Abstract: Embodiments of the present disclosure are specifically related to LLDPE compositions produced from heterogeneous procatalyst compositions and blown and cast films incorporating these LLDPE compositions.
    Type: Application
    Filed: May 29, 2020
    Publication date: July 14, 2022
    Applicant: Dow Global Technologies LLC
    Inventors: Teresa P. Karjala, Kurt F. Hirsekorn, Marlos Giuntini de Oliveira, Gregory J. Brennan, Elva L. Lugo, Yongchao Zeng, Brayden E. Glad, Jon W. Hobson, Linfeng Chen
  • Publication number: 20220197878
    Abstract: Systems, apparatuses, and methods for implementing a collapsed stack are disclosed. A parallel processor includes a plurality of compute units for executing wavefronts of a given application. Each compute unit includes multiple single-instruction, multiple-data (SIMD) units. When the work-items executing on the execution lanes of a SIMD unit are writing data values to a stack, many of the data values are repeated. In these cases, when the lanes are pushing duplicate data values to the stack, a control unit deduplicates the duplicate data values and stores the deduplicated data values. The control unit then generates a control word that maps the deduplicated data values to execution lanes and stores the control word in association with the stored data values. When the stored data values are restored, the control word is used to determine which lanes receive which values of the stored data values.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Matthäus G. Chajdas, Christopher J. Brennan
  • Patent number: 11339528
    Abstract: A mat washer is disclosed which includes a mainframe, a rail surface affixed to the mainframe at an angle of 25 degrees to 90 degrees, a conveying system adapted to transport one or more mats along the rail surface, an enclosed washing chamber having one or more spray bars adapted to direct jets of water at each mat, a discharge wheel adapted for stacking each mat onto a discharge rack, a water recycling system having a waste conveyor adapted to separate large debris from water, the water recycling system have one or more filtration devices adapted to separate small debris from water, and a high pressure pump to supply water under pressure to the one or more spray bars.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: May 24, 2022
    Assignee: Well Service Group Inc.
    Inventors: Richard J. Brennan, William R. Woessner, III
  • Publication number: 20220101560
    Abstract: Systems, apparatuses, and methods for converting pixel data to a custom swizzle mode are disclosed. A graphics engine receives data in a pre-defined swizzle mode. The graphics engine determines a custom swizzle mode for the data that has directionality aligned to the data itself to further optimize deltas that are used for compressing the data. The graphics engine groups incoming data into group of two neighboring pixels in both the horizontal and vertical directions. The graphics engine scores horizontal and vertical groupings against each other to make a first swizzle mode bit selection. Then the graphics engine increases the grouping of pixels to include additional pixels and scores the increased groupings against each other to make subsequent swizzle mode bit selections. The data is reswizzled into the custom swizzle mode and provided to a compressor to be compressed.
    Type: Application
    Filed: December 23, 2020
    Publication date: March 31, 2022
    Inventors: Nooruddin Ahmed, Anthony Chan, Christopher J. Brennan
  • Publication number: 20220101563
    Abstract: Systems, apparatuses, and methods for implementing automatic data format detection techniques are disclosed. A graphics engine receives data of indeterminate format and the graphics engine predicts an organization of the data. As part of the prediction, the graphics engine predicts the pixel depth (i.e., bytes per pixel (BPP)) and format separately. The graphics engine folds the data along pixel and channel boundaries to help in determining the pixel depth and format. The graphics engine scores modes against each other to generate different predictions for different formats. Then, the graphics engine generates scores for the predictions to determine which mode has a highest correlation with the input data. Next, the graphics engine chooses the format which attains the best score among the scores that were generated for the different modes. Then, the graphics engine compresses the unknown data using the chosen format with the best score.
    Type: Application
    Filed: October 30, 2020
    Publication date: March 31, 2022
    Inventors: Anthony Chan, Nooruddin Ahmed, Christopher J. Brennan, Bernard T. K. Chan
  • Publication number: 20220084707
    Abstract: A system and method for producing radioisotopes such as molybdenum-99. The system comprises a first accelerator, a second accelerator, a first beamline, a second beamline, and a target. Using a pair of accelerators, beamlines are preferably fired at a target from opposite directions, thereby irradiating the target from both sides. The system can further comprise a target cooling system utilizing gaseous helium, a modular local target shielding comprised of boxes of either metal shot with liquid coolant or steel with concrete, and a hot cell for loading and unloading target disks.
    Type: Application
    Filed: August 17, 2021
    Publication date: March 17, 2022
    Inventors: James T. Harvey, Rimas S. Milunas, Daniel E. Peltier, Sarah M. Burns, James L. McCarter, Tomas A. Montenegro, Jason M. Schlough, Maxwell J. Brennan, Quintin G. Schiller
  • Patent number: 11272854
    Abstract: The present disclosure provides an impedance measurement circuit for measuring and detecting variations in an impedance under test, and methods of operating the impedance measurement circuit. The impedance measurement circuit comprises a plurality of converts, including at least two digital-to-analog converters (DACs). The DACs together alternate between a first mode of operation and a second mode of operation. In the first mode, a first one of the DACs is operational to convert a first digital input signal to a first analog output using a first hardware component, and a second one of the DACs is operational to convert a second digital input signal to a second analog output using a second hardware component.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: March 15, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Thomas J. Tansley, Colin G. Lyden, Oliver J. Brennan
  • Publication number: 20220061690
    Abstract: The present disclosure provides an impedance measurement circuit for measuring and detecting variations in an impedance under test, and methods of operating the impedance measurement circuit. The impedance measurement circuit comprises a plurality of converts, including at least two digital-to-analog converters (DACs). The DACs together alternate between a first mode of operation and a second mode of operation. In the first mode, a first one of the DACs is operational to convert a first digital input signal to a first analog output using a first hardware component, and a second one of the DACs is operational to convert a second digital input signal to a second analog output using a second hardware component.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 3, 2022
    Inventors: Thomas J. Tansley, Colin G. Lyden, Oliver J. Brennan
  • Publication number: 20220068012
    Abstract: Systems, apparatuses, and methods for executing a shader core instruction to invoke depth culling are disclosed. A shader core executes an instruction to invoke a culling function on a depth culling unit for one or more entities prior to completing a corresponding draw call. The shader core provides a mode and coordinates to the depth culling unit as a result of executing the instruction. The depth culling unit implements the culling function to access a live depth buffer to determine whether one or more primitives corresponding to the entities are occluded. The culling unit returns indication(s) to the shader core regarding the result(s) of processing the one or more primitives. For example, if the results indicate a primitive is occluded, the shader core cancels the draw call for the primitive.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Inventors: Matthäus G. Chajdas, Christopher J. Brennan
  • Patent number: D950987
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: May 10, 2022
    Inventors: Conor J. Brennan, David A. White