Abstract: Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a plurality of singulated microelectronic dies to a removable support member with an active side of the individual dies facing toward the support member, depositing a flowable material onto the dies and a portion of the removable support member such that the flowable material covers a back side of the individual dies and is disposed between adjacent dies, and removing the support member from the active sides of the dies.

Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate. Also disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.

Abstract: Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.

Abstract: Methods for forming and attaching covers to microelectronic imaging units, packaging microelectronic imagers at the wafer level, and microelectronic imagers having covers that protect the image sensor are disclosed herein. In one embodiment, a method includes providing a first substrate having a plurality of covers, the covers including windows comprising regions of the first substrate and stand-offs projecting from the windows. The method continues by providing a second substrate having a plurality of microelectronic dies with image sensors, integrated circuits electrically coupled to the image sensors, and terminals electrically coupled to the integrated circuits. The method includes assembling the covers with corresponding dies so that the windows are aligned with corresponding image sensors and stand-offs contact corresponding dies inboard of the terminals and outboard of the image sensors.

Abstract: A semiconductor die includes a substantially oxide-free metal layer on at least a portion of a surface thereof. The substantially oxide-free metal may enhance adhesion of a packaging material, or mold compound, to the semiconductor die, prevent the occurrence of voids or presence of moisture between the packaging material and the adjacent surface of the semiconductor die, or otherwise prevent delamination of the packaging material from the adjacent surface of the semiconductor die. The substantially oxide-free metal may be copper, palladium, another substantially oxide-free metal, or a combination of substantially oxide-free metals.

Abstract: A microelectronic device and method for manufacture. In one embodiment, two microelectronic substrates are directly bonded to each other without an intermediate adhesive material. For example, each microelectronic substrate can include a first surface, a second surface opposite the first surface, and a functional microelectronic feature coupled to a connection terminal of the microelectronic substrate. The connection terminals can be coupled to a support member, such as a leadframe or a printed circuit board, with the bond plane between the microelectronic substrates either aligned with or transverse to the support member. The microelectronic substrates can be enclosed in a protective packaging material that can include a transparent window to allow selected radiation to strike one or the other of the microelectronic substrates.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound package during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.