Abstract: An electronic device may include a substrate, a seed layer on the substrate, a barrier layer on the seed layer opposite the substrate, and an oxidation barrier on the barrier layer opposite the seed layer. The barrier layer and the seed layer comprise different materials, and the oxidation barrier and the barrier layer may comprise different materials. The seed layer may be undercut relative to the barrier layer and/or relative to the oxidation barrier so that the barrier layer and/or the oxidation barrier define a lip extending beyond the seed layer in a direction parallel with respect to a surface of the substrate. Related methods are also discussed.

Abstract: A method includes forming a patterned resist layer comprising a resist layer opening overlying a bond pad of a substrate. The resist layer opening is at least partially filled with a first solder component layer. A second solder component layer is formed on the first solder component layer. The patterned resist layer is removed. The first solder component layer and the second solder component layer are reflowed to form a lead free binary metal alloy solder bump electrically connected to the bond pad.

Abstract: An electronic device may include a substrate, a seed layer on the substrate, a barrier layer on the seed layer opposite the substrate, and an oxidation barrier on the barrier layer opposite the seed layer. The barrier layer and the seed layer comprise different materials, and the oxidation barrier and the barrier layer may comprise different materials. The seed layer may be undercut relative to the barrier layer and/or relative to the oxidation barrier so that the barrier layer and/or the oxidation barrier define a lip extending beyond the seed layer in a direction parallel with respect to a surface of the substrate. Related methods are also discussed.

Abstract: An electronic device may include an electronic substrate, and an under bump seed metallurgy layer on the electronic substrate. A barrier layer may be provided on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, and the barrier layer may include nickel and/or copper. Moreover, portions of the under bump seed metallurgy layer may be undercut relative to portions of the barrier layer. In addition, a solder layer may be provided on the barrier layer so that the barrier layer is between the solder layer and the under bump seed metallurgy layer.

Abstract: Forming an electronic structure may include forming a seed layer on a substrate, and forming a mask on the seed layer. The mask may include an aperture therein exposing a portion of the seed layer, and a barrier layer may be formed on the exposed portion of the seed layer. A bump may be formed on the barrier layer, and the mask may be removed. In addition, portions of the seed layer may be selectively removed using the barrier layer as an etch mask.

Abstract: Metallurgy structures for input/output pads of an electronic devices can be adapted to receive both solder and wire bonds. First and second metallurgy structures, for example, can be provided on respective first and second input/output pads of an electronic device such that the first and second common metallurgy structures have a shared structure adapted to receive both solder and wire bonds. A solder bond can thus be applied to the first metallurgy structure, and a wire bond can be applied to the second metallurgy structure.

Abstract: An electronic device may include an electronic substrate, and an under bump seed metallurgy layer on the electronic substrate. A barrier layer may be provided on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, and the barrier layer may include nickel and/or copper. Moreover, portions of the under bump seed metallurgy layer may be undercut relative to portions of the barrier layer. In addition, a solder layer may be provided on the barrier layer so that the barrier layer is between the solder layer and the under bump seed metallurgy layer.

Abstract: Methods may be provided for forming an electronic device including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad. In particular, a conductive structure may be formed on the insulating layer and on the exposed portion of the conductive pad. The conductive structure may include a base layer of titanium-tungsten (TiW) and a conduction layer of at least one of aluminum and/or copper. Moreover, the base layer of the conductive structure may be between the conduction layer and the insulating layer. Related devices are also discussed.

Abstract: Methods of forming an electronic device may include forming an under bump seed metallurgy layer on an electronic substrate. A nickel layer may be formed on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the nickel layer and the electronic substrate, and portions of the under bump seed metallurgy layer may be free of the nickel layer. In addition, a solder layer may be formed on the nickel layer so that the nickel layer is between the solder layer and the under bump seed metallurgy layer. In addition, a copper layer may be formed on the under bump seed metallurgy layer before forming the nickel layer with portions of the under bump seed metallurgy layer being free of the copper layer. Accordingly, the under bump seed metallurgy layer may be between the copper layer and the electronic substrate, and the copper layer may be between the under bump seed metallurgy layer and the nickel layer. Related structures are also discussed.

Abstract: Forming an electronic structure may include forming a seed layer on a substrate, and forming a mask on the seed layer. The mask may include an aperture therein exposing a portion of the seed layer, and a barrier layer may be formed on the exposed portion of the seed layer. A bump may be formed on the barrier layer, and the mask may be removed. In addition, portions of the seed layer may be selectively removed using the barrier layer as an etch mask.

Abstract: Forming an electronic structure may include forming a seed layer on a substrate, and forming a mask on the seed layer. The mask may include an aperture therein exposing a portion of the seed layer, and a barrier layer may be formed on the exposed portion of the seed layer. A bump may be formed on the barrier layer, and the mask may be removed. In addition, portions of the seed layer may be selectively removed using the barrier layer as an etch mask.

Abstract: A method of forming an electronic structure may include providing a substrate having a metal pad thereon. A conductive barrier layer may be formed on a first portion of the metal pad, and a second exposed portion of the metal pad may be free of the conductive barrier layer. In addition, an interconnection structure may be provided on the conductive barrier layer with the conductive barrier layer being between the interconnection structure and the metal pad. Moreover, the interconnection structure and the conductive barrier layer may include different materials. Related structures are also discussed.

Abstract: Methods may be provided for forming an electronic device including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad. In particular, a conductive structure may be formed on the insulating layer and on the exposed portion of the conductive pad. The conductive structure may include a base layer of titanium-tungsten (TiW) and a conduction layer of at least one of aluminum and/or copper. Moreover, the base layer of the conductive structure may be between the conduction layer and the insulating layer. Related devices are also discussed.

Abstract: Metallurgy structures for input/output pads of an electronic devices can be adapted to receive both solder and wire bonds. First and second metallurgy structures, for example, can be provided on respective first and second input/output pads of an electronic device such that the first and second common metallurgy structures have a shared structure adapted to receive both solder and wire bonds. A solder bond can thus be applied to the first metallurgy structure, and a wire bond can be applied to the second metallurgy structure.

Abstract: Metallurgy structures for input/output pads of an electronic devices can be adapted to receive both solder and wire bonds. First and second metallurgy structures, for example, can be provided on respective first and second input/output pads of an electronic device such that the first and second common metallurgy structures have a shared structure adapted to receive both solder and wire bonds. A solder bond can thus be applied to the first metallurgy structure, and a wire bond can be applied to the second metallurgy structure.

Abstract: Metallurgy structures for input/output pads of an electronic devices can be adapted to receive both solder and wire bonds. First and second metallurgy structures, for example, can be provided on respective first and second input/output pads of an electronic device such that the first and second common metallurgy structures have a shared structure adapted to receive both solder and wire bonds. A solder bond can thus be applied to the first metallurgy structure, and a wire bond can be applied to the second metallurgy structure.

Abstract: In an isolation trench in a silicon-on-insulator wafer, the sidewalls of the trench curve outwardly at the bottom of the trench where the top silicon layer meets the underlying oxide insulating layer. This sidewall geometry eliminates the sharp corner at the bottom of the trench. Preferably, the top edge of the trench wall is also curved.

Abstract: A low copper concentration multilayered, device interconnect metallurgy, comprises an aluminum-copper (<2 weight percent copper) conductor having formed on one of its surfaces a layer of an intermetallic compound formed from a Group IVA metal and aluminum from the aluminum-copper conductor. The intermetallic compound is formed so as to contain only the single phase line compound of the intermetallic compound.