Abstract: A temperature sensor device and method of sensing temperature are disclosed. The device and method include generating a reference voltage inversely correlated to the temperature, generating a plurality of analysis voltages correlated to the temperature using a reference current, comparing the reference voltage to each of the plurality of analysis voltages, and generating a temperature estimate based on the comparison. The device and method may also include a method to selectively bypass various resistors in a resistor stack used to generate the various analysis voltages. Another embodiment of the present invention comprises a semiconductor device including at least one temperature sensor according to the invention described herein. The temperature sensor and method of sensing temperature may be incorporated into a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

Abstract: A temperature sensor device and method of sensing temperature are disclosed. The device and method include generating a reference voltage inversely correlated to the temperature, generating a plurality of analysis voltages correlated to the temperature using a reference current, comparing the reference voltage to each of the plurality of analysis voltages, and generating a temperature estimate based on the comparison. The device and method may also include a method to selectively bypass various resistors in a resistor stack used to generate the various analysis voltages. Another embodiment of the present invention comprises a semiconductor device including at least one temperature sensor according to the invention described herein. The temperature sensor and method of sensing temperature may be incorporated into a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

Abstract: The invention provides a memory access system and method of operation particularly useful with electronic storage devices having two or more memory units. Accessing of the memory units occurs one at a time and takes place using shared resources, such as shared row and column decoders. In a preferred embodiment, the invention permits the parallel reading of data from one memory unit of a plurality of memory units during a single system clock cycle using shared resources to perform addressing (e.g., read or write access) for the memory unit. The same shared resources are then used by any one of the other memory units during a subsequent system clock cycle to perform its own access function. By reading (or writing) data from (or to) one memory unit only during a single system clock cycle, the shared row and column decoders (and their attendant address lines) become available in a subsequent system clock cycle for use by another memory unit.