Patents by Inventor J. Dennis Keller
J. Dennis Keller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7192829Abstract: Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.Type: GrantFiled: July 17, 1998Date of Patent: March 20, 2007Assignee: Micron Technology, Inc.Inventors: J. Dennis Keller, Roger R. Lee
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Patent number: 7057285Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.Type: GrantFiled: August 30, 2004Date of Patent: June 6, 2006Assignee: Micron Technology, Inc.Inventors: Ruojia Lee, Ralph Kauffman, J. Dennis Keller
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Patent number: 6791141Abstract: Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.Type: GrantFiled: October 13, 1998Date of Patent: September 14, 2004Assignee: Micron Technology, Inc.Inventors: J. Dennis Keller, Roger R. Lee
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Patent number: 6787428Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.Type: GrantFiled: June 26, 2002Date of Patent: September 7, 2004Assignee: Micron Technology, Inc.Inventors: Ruojia Lee, Ralph Kauffman, J. Dennis Keller
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Patent number: 6720605Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.Type: GrantFiled: August 29, 2000Date of Patent: April 13, 2004Assignee: Micron Technology, Inc.Inventors: Ruojia Lee, Ralph Kauffman, J. Dennis Keller
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Publication number: 20020177272Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.Type: ApplicationFiled: June 26, 2002Publication date: November 28, 2002Inventors: Ruojia Lee, Ralph Kauffman, J. Dennis Keller
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Patent number: 6465319Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminium interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.Type: GrantFiled: August 29, 2000Date of Patent: October 15, 2002Assignee: Micron Technology, Inc.Inventors: Ruojia Lee, Ralph Kauffman, J. Dennis Keller
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Publication number: 20010021549Abstract: Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.Type: ApplicationFiled: July 17, 1998Publication date: September 13, 2001Inventors: J. DENNIS KELLER, ROGER R. LEE
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Patent number: 6165863Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.Type: GrantFiled: June 22, 1998Date of Patent: December 26, 2000Assignee: Micron Technology, Inc.Inventors: Ruojia Lee, Ralph Kauffman, J. Dennis Keller
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Patent number: 5985719Abstract: A method of reducing undesired electron depletion through sidewalls of a floating gate of a floating gate transistor comprising providing a non-oxide or oxynitride layer over said sidewalls. Integrated circuitry including a non-volatile field effect transistor includes, a) a floating gate transistor having a gate construction and a pair of opposing source/drain regions, the gate construction having at least one sidewall; b) a shielding layer over the gate sidewall; and c) a dielectric layer on the shielding layer, the dielectric layer being of a different material than the shielding layer. The shielding layer might be provided over an oxide layer previously provided on sidewalls of the gate construction. The shielding layer might be provided over sidewall spacers previously provided relative to sidewalls of the gate construction. Example and preferred shielding layer materials include Si.sub.3 N.sub.4, oxynitride compounds, and aluminum.Type: GrantFiled: November 24, 1997Date of Patent: November 16, 1999Assignee: Micron Technology, Inc.Inventors: J. Dennis Keller, Roger R. Lee
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Patent number: 5726471Abstract: A method of reducing undesired electron depletion through sidewalls of a floating gate of a floating gate transistor comprising providing a non-oxide or oxynitride layer over said sidewalls. Integrated circuitry including a non-volatile field effect transistor includes, a) a floating gate transistor having a gate construction and a pair of opposing source/drain regions, the gate construction having at least one sidewall; b) a shielding layer over the gate sidewall; and c) a dielectric layer on the shielding layer, the dielectric layer being of a different material than the shielding layer. The shielding layer might be provided over an oxide layer previously provided on sidewalls of the gate construction. The shielding layer might be provided over sidewall spacers previously provided relative to sidewalls of the gate construction. Example and preferred shielding layer materials include Si.sub.3 N.sub.4, oxynitride compounds, and aluminum.Type: GrantFiled: November 4, 1996Date of Patent: March 10, 1998Assignee: Micron Technology, Inc.Inventors: J. Dennis Keller, Roger R. Lee
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Patent number: 5707898Abstract: A method of reducing undesired electron depletion through sidewalls of a floating gate of a floating gate transistor comprising providing a non-oxide or oxynitride layer over said sidewalls. Integrated circuitry including a non-volatile field effect transistor includes, a) a floating gate transistor having a gate construction and a pair of opposing source/drain regions, the gate construction having at least one sidewall; b) a shielding layer over the gate sidewall; and c) a dielectric layer on the shielding layer, the dielectric layer being of a different material than the shielding layer. The shielding layer might be provided over an oxide layer previously provided on sidewalls of the gate construction. The shielding layer might be provided over sidewall spacers previously provided relative to sidewalls of the gate construction. Example and preferred shielding layer materials include Si.sub.3 N.sub.4, oxynitride compounds, and aluminum.Type: GrantFiled: April 1, 1996Date of Patent: January 13, 1998Assignee: Micron Technology, Inc.Inventors: J. Dennis Keller, Roger R. Lee
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Patent number: 5292681Abstract: Disclosed is fabricating a semiconductor wafer to form a memory array and peripheral area, the array comprising nonvolatile memory devices employing floating gate transistors and the peripheral area comprising CMOS transistors. A first layer of conductive material is applied atop insulating layers. A dielectric layer is applied atop the first conductive layer for use in floating gate transistors within the array. The dielectric layer and first conductive material are etched from the peripheral area, leaving patterned dielectric material and first conductive material in the array. A second layer of conductive material is applied atop the wafer to cover the peripheral area and dielectric layer of the array. The conductive and dielectric materials of the array are patterned and etched separately from the patterning and etching of conductive material of each of the first and second conductivity type CMOS transistors of the peripheral area.Type: GrantFiled: September 16, 1993Date of Patent: March 8, 1994Assignee: Micron Semiconductor, Inc.Inventors: Roger R. Lee, Tyler A. Lowrey, Fernando Gonzalez, J. Dennis Keller