Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

Abstract: A method and system comprises extracting resources required to run a discrete test case or set of associated test cases on a design. The method and system further includes building a simulation model based on the extracted resources and executing the simulation model using only the extracted resources, exclusive of an entire design, to test a specific function or group of interrelated functions represented by the discrete test case or set of associated test cases for design verification, and correlating the simulation results with the test plan.

Abstract: Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g.

Abstract: A processing system is disclosed for conducting various processes on substrates, such as semiconductor wafers by varying the exposure to a chemical ambient. The processing system includes a processing region having an inlet and an outlet for flowing fluids through the chamber. The outlet is in communication with a conductance valve that is positioned in between the processing region outlet and a vacuum exhaust channel. The conductance valve rapidly oscillates or rotates between open and closed positions for controlling conductance through the processing region. This feature is coupled with the ability to rapidly pulse chemical species through the processing region while simultaneously controlling the pressure in the processing region. Of particular advantage, the conductance valve is capable of transitioning the processing region through pressure transitions of as great as 100:1 while chemical species are flowed through the processing region using equally fast control valves in a synchronous pulsed fashion.

Abstract: A landing gear assembly comprises a landing gear strut assembly further comprising a landing gear strut having a longitudinal axis and extending from an inboard end to an outboard end capable of attaching to a wheel, and a landing gear housing. The landing gear housing has a longitudinal axis coincident with the landing gear strut longitudinal axis and having an interior chamber capable of accepting a portion of the landing gear strut. The landing gear housing is capable of pivotably coupling to an aircraft. The landing gear assembly further comprises a retraction linkage having an inboard end capable of coupling to the aircraft and an outboard end coupled to the landing gear housing. The retraction linkage is moveable to retract the landing gear strut assembly into an aircraft landing gear compartment about the landing gear housing pivotable aircraft coupling.

Abstract: A multi-station workpiece processing system provides a targeted equal share of a regulated input process gas flow to each active processing station of a plurality of active processing stations using a single gas flow regulator for each gas and irrespective of the number of inactive processing stations.

Abstract: As part of a system for processing workpieces, a workpiece support arrangement, separate from a process chamber arrangement supports at least two workpieces at least generally in a stacked relationship to form a workpiece column. A transfer arrangement transports at least two of the workpieces between the workpiece column and the process chamber arrangement by simultaneously moving the two workpieces at least generally along first and second transfer paths, respectively, that are defined between the workpiece column and the first and second process stations. The transfer arrangement can simultaneously move untreated and treated workpieces. Vertical motion swing arms and coaxial swing arms are described. A pair of spaced apart swing arms, the workpiece column and the processing stations can cooperatively define a pentagonal shape. Timing belt backlash elimination, a dual degree of freedom slot valve and low point chamber pumping, for removing chamber contaminants, are also described.

Abstract: A workpiece support is disclosed defining a workpiece-receiving surface. The workpiece support includes a plurality of fluid zones. A fluid, such as a gas, is fed to the fluid zones for contact with a workpiece on the workpiece support. The fluid can have selected thermoconductivity characteristics for controlling the temperature of the workpiece at particular locations. In accordance with the present disclosure, at least certain of the fluid zones are at different azimuthal positions. In this manner, the temperature of the workpiece can be adjusted not only in a radial direction but also in an angular direction.

Abstract: These inventions related to systems and methods for producing, shipping, distributing, and storing hydrogen. In one embodiment, a hydrogen production and storage system includes a plurality of wind turbines for generating electrical power; a power distribution control system for distributing, and converting the electrical power from the wind turbines, a water desalination and/or purification unit which receives and purifies seawater, and an electrolyzer unit that receive electrical power from the power distribution system and purified water from the desalination units and thereby converts the water into hydrogen and oxygen. After its production, hydrogen is stored, transported, and distributed in accordance with various embodiments.

Abstract: An EAS device, and methods for making the device for tuning the resonant frequency of the same is disclosed. The EAS device includes: an outer inductor having one end coupled to a linear or nonlinear capacitor plate; an inner inductor having one end coupled to the other type of capacitor; a first dielectric film on the outer and inner inductors and the capacitor plates coupled thereto, having openings exposing other ends of the outer and inner inductors; a second linear capacitor plate on the dielectric film; a second nonlinear capacitor plate on the dielectric film; a second dielectric film containing holes for the second linear and nonlinear capacitor plates, and exposing the other ends of the first and second inductors; and first and second conducting straps on the second dielectric film, configured to electrically connect one of the exposed inductor ends to a corresponding second capacitor plate.

Abstract: An apparatus and method are described for processing workpieces in a treatment process. A multi-wafer chamber defines a chamber interior including at least two processing stations within the chamber interior such that the processing stations share the chamber interior. Each processing station includes a plasma source and a workpiece pedestal for exposing one of the workpieces to the treatment process using a respective plasma source. The chamber includes an arrangement of one or more electrically conductive surfaces that are asymmetrically disposed about the workpiece at each processing station in a way which produces a given level of uniformity of the treatment process on a major surface of each workpiece. A shield arrangement provides an enhanced uniformity of exposure of the workpiece to the respective one of the plasma sources that is greater than the given level of uniformity that would be provided in an absence of the shield arrangement.

Abstract: Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

Abstract: Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

Abstract: Process and system for processing wafer-shaped objects, such as semiconductor wafers is disclosed. In accordance with the present disclosure, a multiple of two wafers are processed in a thermal processing chamber. The thermal processing chamber is in communication with at least one heating device for heating the wafers. The wafers are placed in the thermal processing chamber in a face-to-face configuration or in a back-to-back configuration.

Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

Abstract: A development system for developing new peripheral software code for new peripheral hardware that will be used in a new integrated system. The development system includes a legacy, or preexisting, integrated system substantially the same as the new integrated system. A model of the new peripheral hardware is made. Each I/O register of the model is mapped into memory-mapped I/O space. Development code corresponding to the new peripheral software code is executed on the preexisting hardware so as to interact with the model via the memory-mapped I/O space. In one embodiment, the model is executed as an embedded model on the preexisting integrated system. In another embodiment, the model is executed as a non-embedded model on a hardware descriptive language simulator.

Abstract: A RF MOS- or nonlinear device-based surveillance and/or identification tag, and methods for its manufacture and use. The tag generally includes (a) an inductor, (b) a first capacitor plate coupled to the inductor, (c) a dielectric film on the first capacitor plate, (d) a semiconductor component on the dielectric film, and (e) a conductor that provides electrical communication between the semiconductor component and the inductor. The method of manufacture generally includes (1) depositing a semiconductor material (or precursor) on a dielectric film; (2) forming a semiconductor component from the semiconductor material/precursor; (3) forming a conductive structure at least partly on the semiconductor component; and (4) etching the electrically functional substrate to form (i) an inductor and/or (ii) a second capacitor plate.

Abstract: A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.

Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

Abstract: A system for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.