Abstract: Hybrid digital-analog computer parallel processing apparatus wherein a template circuit, or multiplicity thereof, is connected to receive parallel digital inputs, each template circuit having controlled current sources with control gates connected respectively to parallel digital inputs. Current sub-sources for each pixel normally have programmable current output and "0" or "1" responses. Each template circuit has a current summing device for algebraically adding the current outputs of current sources, while a greatest value is detected at a comparator which may have a ramp signal applied to another input thereby identifying which template produced a maximum indication from the same parallel inputs. A self-calibrating feedback controlled current generator supplies all current sources on a chip making it possible to generate a known comparator input independent of IC resistivity or other parameters.