Patents by Inventor J. E. Bracken

J. E. Bracken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9715570
    Abstract: Systems and methods are provided for analyzing a via. A physical representation of a via intersecting with an upper layer and a lower layer is received, the physical representation comprising: (i) a pair of pad dimensions comprising an upper pad dimension a1 and a lower pad dimension a2, and/or (ii) a pair of anti-pad dimensions comprising an upper anti-pad dimension b1 and a lower anti-pad dimension b2, where at least one of first and second conditions: (A) the first condition being a1 is different than a2, and (B) the second condition being b1 is different than b2, is true. A determination is made as to which, if any, of the conditions are true. At least one model parameter is selected based on the determination. An admittance parameter corresponding to a section of the via located between the upper and lower layers is computed using the selected model parameter.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: July 25, 2017
    Assignee: Ansys, Inc.
    Inventors: Guangran Zhu, Werner Thiel, J. E. Bracken
  • Patent number: 9715567
    Abstract: Systems and methods are provided for generating an equivalent circuit model. RLGC parameters representing a segment of a layered structure of a specified length are received. The layered structure includes two conductors (also called planes) and at least one trace or a transmission line located between the two conductors. An admittance matrix corresponding to the segment is computed based at least in part on the received RLGC parameters. One or more loading parameters representing a loading of one of the two conductors due to the trace or traces are also computed, and a segment circuit model for the segment of the layered structure based at least in part on the admittance matrix and the one or more loading parameters.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: July 25, 2017
    Assignee: Ansys, Inc.
    Inventors: Xin Xu, J. E. Bracken, Werner Thiel