Patents by Inventor J. Edwin Hostetter
J. Edwin Hostetter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9865514Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.Type: GrantFiled: March 10, 2015Date of Patent: January 9, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Hanyi Ding, J. Edwin Hostetter, Ping-Chuan Wang, Kimball M. Watson
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Publication number: 20150187667Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.Type: ApplicationFiled: March 10, 2015Publication date: July 2, 2015Applicant: International Business Machines CorporationInventors: Hanyi Ding, J. Edwin Hostetter, Ping-Chuan Wang, Kimball M. Watson
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Patent number: 9059204Abstract: A method and apparatus for repairing transistors may include applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time. In this manner the transistor structure may be repaired or returned to operate at or near the original operating characteristics.Type: GrantFiled: April 28, 2014Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Kai D. Feng, J. Edwin Hostetter, Jr., Ping-Chuan Wang, Zhijian Yang
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Patent number: 9059051Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.Type: GrantFiled: May 8, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Hanyi Ding, J. Edwin Hostetter, Jr., Ping-Chuan Wang, Kimball M. Watson
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Publication number: 20140332973Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.Type: ApplicationFiled: May 8, 2013Publication date: November 13, 2014Applicant: International Business Machines CorporationInventors: Hanyi Ding, J. Edwin Hostetter, JR., Ping-Chuan Wang, Kimball M. Watson
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Publication number: 20140234990Abstract: A method and apparatus for repairing transistors may include applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time. In this manner the transistor structure may be repaired or returned to operate at or near the original operating characteristics.Type: ApplicationFiled: April 28, 2014Publication date: August 21, 2014Applicant: International Business Machines CorporationInventors: Kai D. Feng, J. Edwin Hostetter, JR., Ping-Chuan Wang, Zhijian Yang
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Patent number: 8159814Abstract: Embodiments of the present invention provide a semiconductor device that includes a transistor device having a first, a second, and a third node; and an interconnect structure having at least one wire and the wire having a first and a second end with the first end of the wire being connected to one of the first, the second, and the third node of the transistor device. The wire is conductive and adapted to provide an operating current in a first direction during a normal operating mode, and adapted to provide a repairing current in a second direction opposite to the first direction during a repair mode of the semiconductor device. In one embodiment the transistor device is a bipolar transistor with the first, second, and third nodes being an emitter, a base, and a collector of the bipolar transistor. The wire is connected to one of the emitter and the collector. Method of operating the semiconductor device and current supplying circuit for the semiconductor device are also disclosed.Type: GrantFiled: January 19, 2009Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Ping-Chuan Wang, Zhijian Yang, Fernando J. Guarin, J. Edwin Hostetter, Kai D Feng
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Patent number: 7919834Abstract: One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.Type: GrantFiled: December 4, 2007Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Robert Edgar Davis, Robert Daniel Edwards, J. Edwin Hostetter, Jr., Ping-Chuan Wang, Kimball M. Watson
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Publication number: 20100182729Abstract: Embodiments of the present invention provide a semiconductor device that includes a transistor device having a first, a second, and a third node; and an interconnect structure having at least one wire and the wire having a first and a second end with the first end of the wire being connected to one of the first, the second, and the third node of the transistor device. The wire is conductive and adapted to provide an operating current in a first direction during a normal operating mode, and adapted to provide a repairing current in a second direction opposite to the first direction during a repair mode of the semiconductor device. In one embodiment the transistor device is a bipolar transistor with the first, second, and third nodes being an emitter, a base, and a collector of the bipolar transistor. The wire is connected to one of the emitter and the collector. Method of operating the semiconductor device and current supplying circuit for the semiconductor device are also disclosed.Type: ApplicationFiled: January 19, 2009Publication date: July 22, 2010Applicant: International Business Machines CorporationInventors: Ping-Chuan Wang, Zhijian Yang, Fernando J. Guarin, J. Edwin Hostetter, Kai D. Feng
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Patent number: 7723824Abstract: A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (VCB of less than 1 V).Type: GrantFiled: May 4, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Fernando Guarin, J. Edwin Hostetter, Jr., Stewart E. Rauch, III, Ping-Chuan Wang, Zhijian J. Yang
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Publication number: 20090140395Abstract: One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Applicant: International Business Machines CorporationInventors: Robert Edgar Davis, Robert Daniel Edwards, J. Edwin Hostetter, JR., Ping-Chuan Wang, Kimball M. Watson
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Patent number: 7238565Abstract: A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (V?CB of less than 1 V).Type: GrantFiled: December 8, 2004Date of Patent: July 3, 2007Assignee: International Business Machines CorporationInventors: Fernando Guarin, J. Edwin Hostetter, Jr., Stewart E. Rauch, III, Ping-Chuan Wang, Zhijian J. Yang