Abstract: A monitoring device for monitoring the well-being of animals, the monitoring device including a carrier arrangement which can be attached to an animal and which has at least one sensor for sensing a vital function of an animal wearing the carrier arrangement. In the event of a deviation of an actual state from a target state of the animal that leaves a tolerance range, an output signal signaling the deviation is outputted by an output unit.

Abstract: A monitoring device for monitoring the well-being of animals, the monitoring device including a carrier arrangement which can be attached to an animal and which has at least one sensor for sensing a vital function of an animal wearing the carrier arrangement. In the event of a deviation of an actual state from a target state of the animal that leaves a tolerance range, an output signal signaling the deviation is outputted by an output unit.

Abstract: A method for packing semiconductor components is provided, in which a first side of a first wafer is connected to at least one further wafer, wherein at least one of the wafers has a plurality a semiconductor circuits and wherein trenches are made in the second side of the first wafer opposite to the first side and divide the first wafer into a plurality of parts, which are separated from one another by the trenches, but are connected mechanically to one another by means of the at least one further wafer, and wherein the connecting region between the first wafer and the at least one further wafer has been or will be laterally exposed in the trenches. A coating that covers the connecting region is then applied to the regions of the trenches in which the connecting region is exposed.

Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.

Abstract: The invention relates to a method for production of packaged electronic, in particular optoelectronic, components in a composite wafer, in which the packaging is carried out by fitting microframe structures of a cover substrate composed of glass, and the composite wafer is broken up along trenches which are produced in the cover substrate, and to packaged electronic components which can be produced using this method, comprising a composite of a mount substrate and a cover substrate, with at least one functional element and at least one bonding element, which makes contact with the functional element, being arranged on the mount substrate, with the cover substrate being a microstructured glass which is arranged on the mount substrate, and forms a cavity above the functional element, and with the bonding elements being located outside the cavity.

Abstract: A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.

Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.

Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.

Abstract: A method for packing semiconductor components is provided, in which a first side of a first wafer is connected to at least one further wafer, wherein at least one of the wafers has a plurality a semiconductor circuits and wherein trenches are made in the second side of the first wafer opposite to the first side and divide the first wafer into a plurality of parts, which are separated from one another by the trenches, but are connected mechanically to one another by means of the at least one further wafer, and wherein the connecting region between the first wafer and the at least one further wafer has been or will be laterally exposed in the trenches. A coating that covers the connecting region is then applied to the regions of the trenches in which the connecting region is exposed.

Abstract: A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.

Abstract: A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.

Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.

Abstract: The invention relates to a method for production of packaged electronic, in particular optoelectronic, components in a composite wafer, in which the packaging is carried out by fitting microframe structures of a cover substrate composed of glass, and the composite wafer is broken up along trenches which are produced in the cover substrate, and to packaged electronic components which can be produced using this method, comprising a composite of a mount substrate and a cover substrate, with at least one functional element and at least one bonding element, which makes contact with the functional element, being arranged on the mount substrate, with the cover substrate being a microstructured glass which is arranged on the mount substrate, and forms a cavity above the functional element, and with the bonding elements being located outside the cavity.

Abstract: The glass is advantageous for microstructuring, especially reactive ion etching with fluorine and fluorine compounds, and has a glass composition based on oxide content and expressed in mol % of: SiO2, 40-70; GeO2, 0-30; B2O3, 5-20; P2O5, 5-20; WO3, 0-10; As2O3, 0-10; Yb2O3, 0-5; and Lu2O3, 0-5. Microstructure components, such as micro arrays, Fresnel lenses, micro wafers, or micro lens wafers, made by a method including reactive ion etching from the glass are also part of the present invention.

Abstract: In the method for microstructuring flat glass substrates a substrate surface of a glass substrate is coated with at least one structured mask layer and subsequently exposed to a chemically reactive ion etching process (RIE) with at least one chemical etching gas. In order to provide the same or a higher quality etching and etching rate even for economical types of glass the chemical etching gas is mixed with at least one noble gas, so that the proportion of sputtering etching in the ion etching process is significantly increased.

Abstract: In the method for microstructuring flat glass substrates a substrate surface of a glass substrate is coated with at least one structured mask layer and subsequently exposed to a chemically reactive ion etching process (RIE) with at least one chemical etching gas. In order to provide the same or a higher quality etching and etching rate even for economical types of glass the chemical etching gas is mixed with at least one noble gas, so that the proportion of sputtering etching in the ion etching process is significantly increased.

Abstract: A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.

Abstract: The glass is advantageous for microstructuring, especially reactive ion etching with fluorine and fluorine compounds, and has a glass composition based on oxide content and expressed in mol % of: SiO2, 40-70; GeO2, 0-30; B2O3, 5-20; P2O5, 5-20; WO3, 0-10; As2O3, 0-10; Yb2O3, 0-5; and Lu2O3, 0-5. Microstructure components, such as micro arrays, Fresnel lenses, micro wafers, or micro lens wafers, made by a method including reactive ion etching from the glass are also part of the present invention.

Abstract: In the method for microstructuring flat glass substrates a substrate surface of a glass substrate is coated with at least one structured mask layer and subsequently exposed to a chemically reactive ion etching process (RIE) with at least one chemical etching gas. In order to provide the same or a higher quality etching and etching rate even for economical types of glass the chemical etching gas is mixed with at least one noble gas, so that the proportion of sputtering etching in the ion etching process is significantly increased.

Abstract: The hybrid housing includes a base housing and one or more separately made functional components joined in the base housing by electron beam welding to provide a hermetically sealed hybrid housing e.g. for use under water or in aircraft or spacecraft. The separately made functional components can included e.g. a KOVAR-glass feed-through device and/or a copper or molybdenum metal block for heat dissipation. The base housing can be made of aluminum, an aluminum alloy, stainless steel or VA steel.