Patents by Inventor J. Eric Bracken

J. Eric Bracken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10097239
    Abstract: Systems and methods are provided for constructing a physical transmission line system. Characteristic data associated with a transmission line system is received. A model of the transmission line system is built based on the characteristic data. Building a model of the transmission line system includes determining a characteristic admittance matrix based on the characteristic data, determining a propagation function matrix based on the characteristic data, calculating a linking matrix based on the characteristic admittance matrix and the propagation function matrix, and determining a state space model based on the characteristic admittance matrix and the linking matrix. A simulation is performed using the state space model to determine a physical characteristic, where the transmission line system is built or modified based on the simulation-determined physical characteristic.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: October 9, 2018
    Assignee: Ansys, Inc.
    Inventors: Michael J. Tsuk, Jacob K. White, J. Eric Bracken
  • Patent number: 8938372
    Abstract: Disclosed are system and methods for simulating signal integrity structures using stable processed modes (e.g., matched traveling-wave power modes), and/or for creating response surfaces from stable response parameters.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: January 20, 2015
    Assignee: SAS IP, Inc.
    Inventors: Lars Eric Rickard Petersson, J. Eric Bracken, John Bosley Manges
  • Patent number: 5313398
    Abstract: A method and apparatus for simulating a microelectronic circuit includes the steps of storing of a microelectronic circuit or system representation in a computer system and then dividing the circuit or system into portions containing nonlinear elements and linear partitions. The linear partitions are then independently solved for by modelling each linear partition using Asymptotic Waveform Evaluation (AWE) to form multiport admittance macromodels. These macromodels provide admittance and current stencils, which may be functions of time, to a global MNA matrix used by SPICE at each time point to simulate the operation of the entire microelectronic circuit. A linearized transient representation for the nonlinear elements is provided as SPICE admittance and current stencils using conventional techniques. By using AWE techniques to solve the linear partitions separately, significant savings in computation time and improved computational storage efficiency can be achieved.
    Type: Grant
    Filed: July 23, 1992
    Date of Patent: May 17, 1994
    Assignee: Carnegie Mellon University
    Inventors: Ronald A. Rohrer, Vivek Raghavan, J. Eric Bracken