Abstract: A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. If a membership function has a boundary with an infinite slope, the slope value is set equal to zero and the degree of membership is then set equal to a saturation value for those input values corresponding to the infinite slope boundary.

Abstract: A data processing system (10) selectively weights a fuzzy logic rule in response to a single "REVW" software instruction. In response to the REVW instruction, the data processing system (10) fetches a set of fuzzy inputs associated with the fuzzy logic rule, and determines a minimum fuzzy input from the set. The data processing system (10) then selectively weights the minimum fuzzy input to provide a fuzzy output of the fuzzy logic rule, by multiplying the minimum fuzzy input by a corresponding weight. In one embodiment, a carry bit in a condition code register (60) determines whether the fuzzy logic rule is to be weighted. In response to the single REVW instruction, the data processing system (10) further performs this selective fuzzy rule weighting operation for all rules in a fuzzy rule base.

Abstract: A circuit (14) to evaluate fuzzy logic rules in a data processor (10) incorporates fuzzy rule weights. A rule strength is stored in a first register (220), while a weight value is stored in a second register (222) in a processor (10). The circuit (14) adds 1 to the weight value before multiplying with the rule value. The product is truncated to produce the weighted rule strength. In the execution unit (14), the rule value is initially applied to one adder (204) input (208), while a bit of the weight value is monitored to determine whether the rule value or 0-bits are inputted to the other adder (204) input (206) which adds the inputs to produce a partial product, which is then fed back to an adder (204) input for the next process cycle wherein the next bit of the weight value is monitored.

Abstract: A process (601-611) and implementing computer system (13) for selecting a specific logic circuit among a group of otherwise acceptable alternative circuits, as represented by prime implicant terms (607), includes determining and assigning a power consumption factor (609) to each of the alternative logic circuit implementations. In the disclosed example, the probability of switching logic states (313, 513) is determined and used as a measure of the power consumption factor associated with each of the acceptable and valid prime implicant solutions for a given logic function. From a group of acceptable prime implicant solutions, the power optimum solution is chosen (611) which has been determined to be the most likely to consume the least amount of power in implementing the desired logic function.

Abstract: A circuit (14) to evaluate a plurality of fuzzy logic rules as executable instructions in a data processor (310). A first instruction retrieves a fuzzy input value from memory (32) and stores it in an accumulator (58). A second instruction retrieves a second fuzzy input value from memory (32) and compares it to the fuzzy input value stored in the accumulator (58). The minimum value of the two fuzzy input values is then allowed to remain in the accumulator (58). Another program instruction retrieves a fuzzy output value from memory (32) and compares it to the value in the accumulator (58). The maximum of these two values is then determined by the instruction and this maximum value is then stored in memory (32).

Abstract: A data processing system for testing a rulebase implemented in a rule evaluation process utilized for transforming fuzzy inputs to fuzzy outputs in a fuzzy logic operation, the rule evaluation process including a plurality of rules, wherein a path in the fuzzy logic operation includes one of the fuzzy inputs specified by the path, one of the plurality of rules specified by the path, and one of the fuzzy outputs specified by the path, wherein the rule evaluation process implements a MIN/MAX method of rule evaluation. The system determines which paths in the fuzzy logic operation can be tested simultaneously, and assigns values to test vectors in order to test the paths in a manner consistent with the determination of which paths in the fuzzy logic operation can be tested simultaneously, wherein paths that can be tested simultaneously can be tested by a same test vector.

Abstract: A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. If a membership function has a boundary with an infinite slope, the slope value is set equal to zero and the degree of membership is then set equal to a saturation value for those input values corresponding to the infinite slope boundary.

Abstract: In a data processing system (10) implementing a fuzzy logic operation, a switching mechanism (802) is implemented to provide a selection between a variable format rule base (803) and a fixed format rule base. The variable format rule base utilizes buffers between fuzzy input addresses and fuzzy output addresses, while the fixed format rule base does not require such buffers since a number of fuzzy input addresses and fuzzy output addresses is predetermined.

Abstract: A data processing system (10) includes an instruction known as the "MEM" instruction which determines a degree of membership of an input value in a fuzzy logic membership function. Additionally in response to the MEM instruction, the data processing system (10) checks whether boundary values defining a boundary of the membership function assume certain predetermined values. If so, this membership function is the final membership function of the set of membership functions, and the data processing system (10) generates a termination signal (151). In one embodiment, the termination signal (151) sets a bit in a condition code register (69) so that a software program loop, which determines the degree of membership of an input value in successive membership functions of the set of membership functions, may be exited.

Abstract: The data processing system(10) implements a resumable instruction using two instruction bytes. When a program counter (72) points to a first instruction byte, a first data processing operation is initiated. If an interrupt occurs during execution of the first data processing operation, intermediate data calculations held in a plurality of temporary registers (64, 66, 68) are saved in stack memory at a location pointed to by the stack pointer register (72). The program counter is incremented to point to a second byte of the instruction. An instruction resume operation is executed and the intermediate results of the data processing operation are accessed from the stack memory and restored to respective storage locations within the data processing system. After the intermediate results are restored, the program counter is decremented to point to the first instruction byte and the instruction continues executing the data processing operation as though no interrupt occurred.

Abstract: A data processing system (10) performs indexed addressing, autoincrementing, and autodecrementing using power of two byte boundaries. For example, a 5-bit offset allows a user to progress sixteen bytes either forward or backward through a table of data. An instruction specifying an operation to be performed, a pointer register (58, 60), and an offset value is provided to an execution unit (14). The pointer register (58, 60) stores a first address value and the offset value has a sign and a magnitude. An arithmetic logic unit, ALU, (52) inverts the sign of the offset value to provide an inverted sign value. A plurality of adders (100, 102, 104, 106, and 108) adds the offset value, the first address value, and the inverted sign value to generate an offset sum. A positive offset value is increased by one to generate a symmetric power of two offset range.

Abstract: A digital timer apparatus incorporates a free running counter, an interval timer, a capture register, a pulse accumulator; holding logic and mode selection logic. In one mode of operation, a rising or falling edge of an external signal causes the current contents of the free running counter to be loaded into the capture register, causes the previous value of the capture register to be transferred to a holding register and causes the pulse accumulator to be incremented. A read of the capture holding register causes the pulse accumulator value to be transferred to a holding register and causes the pulse accumulator to be reset. The output of the interval timer can cause an interrupt signal to be generated to request service from a central processing unit.

Abstract: A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. An operand assignment circuit (50) and an ALU (56) allow circuit (14) to determine the degree of membership more quickly. Assignment circuit (50) determines a multiplier for a multiplication operation based on a number of significant bits in the values to be multiplied. If the multiplier is smaller than the multiplicand, shorter multiplication operations may be performed. Additionally, ALU (56) operates in a split mode of operation which is able to perform two eight bit subtraction or multiplication operations concurrently which also results in these operations being performed more efficiently.

Abstract: A circuit (14) to evaluate a plurality of fuzzy logic rules in a data processor (10) in response to a single "REV" software instruction. The REV instruction evaluates the rules stored in a memory (32) to determine a rule strength of each. Antecedents are separated from consequences of each of the rules by a buffer address. To evaluate the antecedents, an ALU (52) subtracts an antecedent in memory (32) from a current antecedent stored in an accumulator (58). Subsequently, a swap logic (46) provides control information to assign a minimum value as a rule strength of the rule. Similarly, a maximum rule strength is required during evaluation of the consequences. ALU (52) subtracts a consequence in memory (32) from a consequence stored in accumulator (58). Depending on a result, swap logic (46) provides control information to assign a maximum rule strength to the consequences of the evaluated rule.

Abstract: An adder circuit that has an encoded carry input, where a bit position weight of the carry input is two, allows the adder circuit to selectively concurrently add a data value of two to a first and a second input data operand of the adder circuit. The adder circuit is also able to add the first and second input data operands with a second carry input that is not encoded. A recoded multiplier combines two partial product calculations into one calculation during only a first partial product calculation operation by using the adder circuit. Partial product calculations are reduced in number during a multiply operation of a data processor.

Abstract: An adder circuit that has an encoded carry input, where a bit position weight of the carry input is two, allows the adder circuit to selectively concurrently add a data value of two to a first and a second input data operand of the adder circuit. The adder circuit is also able to add the first and second input data operands with a second carry input that is not encoded. A recoded multiplier combines two partial product calculations into one calculation during only a first partial product calculation operation by using the adder circuit. Partial product calculations are reduced in number during a multiply operation of a data processor.