Abstract: An industrial programming method and apparatus, a device, a storage medium, and a program product are provided. In a programming scheme generation method, a programming device obtains a first group of constraints for a plurality of parameters in an industrial programming job. Further, the programming device constructs, based on the first group of constraints, a cut constraint associated with at least one integer parameter in the plurality of parameters, and constructs a second group of constraints based on the cut constraint and the first group of constraints, where a type of the at least one integer parameter in the second group of constraints is changed. The programming device determines values of the plurality of parameters based on the second group of constraints, to generate a programming scheme for the industrial programming job.

Abstract: A package structure is disclosed. The package structure includes a first substrate, a second substrate, a gap, and a directing structure. The second substrate is disposed under the first substrate. The gap is between the first substrate and the second substrate. The gap includes a first region and a second region. The first region is configured to accommodate a filling material. The directing structure is disposed in a flow path of the filling material and configured to reduce a migration of the filling material from the first region to the second region.

Abstract: A projector includes a light sensor, a micromirror device, a light source and a processor. The light sensor senses an ambient brightness. The micromirror device is controlled by a duty cycle. The light source is controlled by a driving current. The processor receives an image including a plurality of non-black pixels. When a brightness of at least one of the non-black pixels is lower than the ambient brightness, the processor increases one of the duty cycle and the driving current. When the brightness of at least one of the non-black pixels is still lower than the ambient brightness after adjustment, the processor increases another one of the duty cycle and the driving current. When the brightness of at least one of the non-black pixels is still lower than the ambient brightness after adjustment, the processor performs an image processing process for the brightness of the non-black pixels.

Abstract: A projector includes a light sensor, a micromirror device, a light source and a processor. The light sensor senses an ambient brightness. The micromirror device is controlled by a duty cycle. The light source is controlled by a driving current. The processor receives an image including a plurality of non-black pixels. When a brightness of at least one of the non-black pixels is lower than the ambient brightness, the processor increases one of the duty cycle and the driving current. When the brightness of at least one of the non-black pixels is still lower than the ambient brightness after adjustment, the processor increases another one of the duty cycle and the driving current. When the brightness of at least one of the non-black pixels is still lower than the ambient brightness after adjustment, the processor performs an image processing process for the brightness of the non-black pixels.

Abstract: According to various embodiments, there is provided a lens sheet including an array of lenses arranged parallel to each other. Each lens includes a light redirecting portion having a light incident surface and a light reflecting surface, and includes a light refracting portion. The light reflecting surface is slanted relative to the light incident surface and relative to a plane interfacing the light redirecting portion and the light refracting portion, such that light of a first view image and light of a second view image transmitted through the light incident surface into the lens are directed to a first region and a second region of the light reflecting surface respectively and are reflected to the light refracting portion by the light reflecting surface. The first region is next to the second region.

Abstract: The present invention relates to a system and method for monitoring and predicting the mental health of a person. Data is collected from multiple sensors including a camera and microphone. Additional sensors can be added to improve the robustness of the system such as heart rate sensors and respiration sensors. The data can be collected in phases that provide contextual awareness to the system. An algorithm can synchronize the data collected in the different phases and the data can be analyzed individually and collectively. Historical data can be included in the analysis to evaluate and predict the mental condition of a person.

Abstract: According to various embodiments, there is provided a lens sheet including an array of lenses arranged parallel to each other. Each lens includes a light redirecting portion having a light incident surface and a light reflecting surface, and includes a light refracting portion. The light reflecting surface is slanted relative to the light incident surface and relative to a plane interfacing the light redirecting portion and the light refracting portion, such that light of a first view image and light of a second view image transmitted through the light incident surface into the lens are directed to a first region and a second region of the light reflecting surface respectively and are reflected to the light refracting portion by the light reflecting surface. The first region is next to the second region.

Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

Abstract: A video-based system detects the position of elevator doors based on video data provided by one or more video detectors. Based on the detected position of the elevator doors, a distance between the elevator doors can be determined. The operation of the elevator doors is controlled based, at least in part, on the detected distance between the elevator doors.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

Abstract: A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop.

Abstract: A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.

Abstract: An integrated circuit structure includes a semiconductor substrate and a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor is in contact with the thyristor.

Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.

Abstract: A lateral heterojunction bipolar transistor (HBT) comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Abstract: DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050° C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.

Abstract: An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

Abstract: This invention provides a circuit and a method for generating a low-level current using semiconductor charge pumping. The invention provides a means of generating a range of current sources by varying the frequency of a repetitive voltage pulse input signal. Also, this invention utilizes one or many MOSFET devices in order to produce higher levels of current. The current source embodiments of this invention generate very stable current sources with high input impedances.