Patents by Inventor J. Jack Ren

J. Jack Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating a flux concentrating system for use in a magnetoelectronics device
    Patent number: 7279341
    Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: October 9, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas V. Meixner, Gregory W. Grynkewich, Jaynal A. Molla, J. Jack Ren, Richard G. Williams, Brian R. Butcher, Mark A. Durlam
  • Cladded conductor for use in a magnetoelectronics device and method for fabricating the same
    Patent number: 7105363
    Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: September 12, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark A. Durlam, Jeffrey H. Baker, Brian R. Butcher, Mark F. Deherrera, John J. D'Urso, Earl D. Fuchs, Gregory W. Grynkewich, Kelly W. Kyler, Jaynal A. Molla, J. Jack Ren, Nicholas D. Rizzo
  • Magnetoelectronic devices utilizing protective capping layers and methods of fabricating the same
    Patent number: 7087972
    Abstract: Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to substantially expose the first conductor. A protective capping layer is deposited by electroless deposition within the via and is electrically coupled to the first conductor. A magnetic memory element layer is formed within the via and overlying the second insulating layer and the second conductor.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: August 8, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: J. Jack Ren, Brian R. Butcher, Mark A. Durlam, Gregory W. Grynkewich
  • Method for fabricating a flux concentrating system for use in a magnetoelectronics device
    Patent number: 6943038
    Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 13, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas V. Meixner, Gregory W. Grynkewich, Jaynal A. Molla, J. Jack Ren, Richard G. Williams, Brian R. Butcher, Mark A. Durlam
  • Cladded conductor for use in a magnetoelectronics device and method for fabricating the same
    Patent number: 6885074
    Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: April 26, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark A. Durlam, Jeffrey H. Baker, Brian R. Butcher, Mark F. Deherrera, John J. D'Urso, Earl D. Fuchs, Gregory W. Grynkewich, Kelly W. Kyler, Jaynal A. Molla, J. Jack Ren, Nicholas D. Rizzo
  • Method of forming a flux concentrating layer of a magnetic device
    Publication number: 20040175845
    Abstract: A method of forming a magnetic device, especially the digit line of a magnetic random access memory (MRAM) device is disclosed. The digit line includes a stack of materials that includes a barrier layer, a seed layer and a soft magnetic layer that is electrochemically deposited. Preferably, the barrier layer and the seed layer are formed by physical vapor deposition (PVD) and the soft magnetic layer is formed by electroless plating. In one embodiment, the barrier layer includes tantalum, the seed layer includes ruthenium and the soft magnetic layer includes nickel and iron.
    Type: Application
    Filed: March 3, 2003
    Publication date: September 9, 2004
    Inventors: Jaynal A. Molla, John J. D'Urso, J. Jack Ren
  • Cladded conductor for use in a magnetoelectronics device and method for fabricating the same
    Publication number: 20040099908
    Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
    Type: Application
    Filed: November 27, 2002
    Publication date: May 27, 2004
    Inventors: Mark A. Durlam, Jeffrey H. Baker, Brian R. Butcher, Mark F. Deherrera, John J. D'Urso, Earl D. Fuchs, Gregory W. Grynkewich, Kelly W. Kyler, Jaynal A. Molla, J. Jack Ren, Nicholas D. Rizzo