Patents by Inventor J. Keith Hodgson

J. Keith Hodgson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11193961
    Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, J. Keith Hodgson, Alexander Lyakhov, Chiu Keung Tang, Narayanan Raghuraman, Narayanan Natarajan
  • Publication number: 20200264214
    Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: Intel Corporation
    Inventors: Gerhard SCHROM, J. Keith HODGSON, Alexander LYAKHOV, Chiu Keung TANG, Narayanan RAGHURAMAN, Narayanan NATARAJAN
  • Patent number: 10641799
    Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), and compensator for a voltage regulator (VR), are provided. In one example, an apparatus includes: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, J. Keith Hodgson, Alexander Lyakhov, Chiu Keung Tang, Narayanan Raghuraman, Narayanan Natarajan
  • Publication number: 20190154739
    Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Gerhard SCHROM, J. Keith HODGSON, Alexander LYAKHOV, Chiu Keung TANG, Narayanan RAGHURAMAN, Narayanan NATARAJAN
  • Patent number: 10184961
    Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, J. Keith Hodgson, Alexander Lyakhov, Chiu Keung Tang, Narayanan Raghuraman, Narayanan Natarajan
  • Patent number: 10033402
    Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Takao Oshita, George L. Geannopoulos, David E. Duarte, J. Keith Hodgson, James S. Ayers, Avner Kornfeld, Jonathan P. Douglas
  • Patent number: 9733282
    Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. are provided here. An apparatus is provided which comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, J. Keith Hodgson, Alexander Lyakhov, Chiu Keung Tang, Narayanan Raghuraman, Narayanan Natarajan
  • Patent number: 9696350
    Abstract: Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Edward A. Burton, Gerhard Schrom, Michael W. Rogers, Alexander Lyakhov, Ravi Sankar Vunnam, Jonathan P. Douglas, Fabrice Paillet, J. Keith Hodgson, William Dawson Kesling, Chiu Keung Tang, Narayanan Raghuraman, Narayanan Natarajan, Samie Samaan, George Geannopoulos
  • Publication number: 20170030947
    Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Application
    Filed: September 26, 2016
    Publication date: February 2, 2017
    Inventors: Gerhard SCHROM, J. Keith Hodgson, Alexander Lyakhov, Chiu Keung Tang, Narayanan Raghuraman, Narayanan Natarajan
  • Publication number: 20170005670
    Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.
    Type: Application
    Filed: September 14, 2016
    Publication date: January 5, 2017
    Inventors: Takao Oshita, George L. Geannopoulos, David E. Duarte, J. Keith Hodgson, James S. Ayers, Avner Kornfeld, Jonathan P. Douglas
  • Patent number: 9520895
    Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: December 13, 2016
    Assignee: Intel Corporation
    Inventors: Takao Oshita, George L. Geannopoulos, David E. Duarte, J Keith Hodgson, James S. Ayers, Avner Kornfeld, Jonathan P. Douglas
  • Publication number: 20160233879
    Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.
    Type: Application
    Filed: May 6, 2015
    Publication date: August 11, 2016
    Inventors: Takao Oshita, George L. Geannopoulos, David E. Duarte, J. Keith Hodgson, James S. Ayers, Avner Kornfeld, Jonathan P. Douglas
  • Patent number: 9065470
    Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Takao Oshita, George L. Geannopoulos, David E. Duarte, J Keith Hodgson, James S. Ayers, Avner Kornfeld, Jonathan P. Douglas
  • Patent number: 9046552
    Abstract: Described is an apparatus to trim on-die passive components. The apparatus comprises: a resistor-capacitor (RC) dominated oscillator independent of first order transistor speed dependency, wherein the RC dominated oscillator including one or more resistors and capacitors with programmable resistance and capacitance, and wherein the RC dominated oscillator to generate an output signal having a frequency depending substantially on values of the programmable resistance and capacitance; and a trim-able resistor or capacitor operable to be trimmed, for compensating process variations, according to a program code associated with the programmable resistance and capacitance of the RC dominated oscillator.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Fabrice Paillet, Gerhard Schrom, Alexander Lyakhov, George L. Geannopoulos, Ravi Sankar Vunnam, J. Keith Hodgson
  • Patent number: 9048851
    Abstract: Described is an apparatus for providing spread-spectrum to a clock signal. The apparatus comprises: an oscillator to generate an output clock signal, the oscillator to receive an adjustable reference signal to adjust frequency of the output clock signal; a first circuit to provide a first signal indicative of a center frequency of the output clock signal; a second circuit to generate a switching waveform to provide spread-spectrum for the output clock signal; and a third circuit, coupled to the first and second circuits, to provide the adjustable reference signal according to the first signal and the switching waveform.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Alexander Lyakhov, Michael W. Rogers, Dawson W. Kesling, Jonathan P. Douglas, J. Keith Hodgson
  • Publication number: 20150069995
    Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Application
    Filed: November 17, 2014
    Publication date: March 12, 2015
    Inventors: Gerhard SCHROM, J. Keith HODGSON, Alexander LYAKHOV, Chiu Keung TANG, Narayanan RAGHURAMAN, Narayanan NATARAJAN
  • Patent number: 8890737
    Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, an apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 18, 2014
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, J. Keith Hodgson, Alexander Lyakhov, Chiu Keung Tang, Narayanan Raghuraman, Narayanan Natarajan
  • Publication number: 20140266119
    Abstract: Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.
    Type: Application
    Filed: May 31, 2013
    Publication date: September 18, 2014
    Inventors: Edward A. BURTON, Gerhard SCHROM, Michael W. ROGERS, Alexander LYAKHOV, Ravi Sankar VUNNAM, Jonathan P. DOUGLAS, Fabrice PAILLET, J. Keith HODGSON
  • Publication number: 20140266832
    Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Application
    Filed: June 28, 2013
    Publication date: September 18, 2014
    Inventors: Gerhard SCHROM, J. Keith HODGSON, Alexander LYAKHOV, Chiu Keung TANG, Narayanan RAGHURAMAN, Narayanan NATARAJAN
  • Publication number: 20140266486
    Abstract: Described is an apparatus to trim on-die passive components. The apparatus comprises: a resistor-capacitor (RC) dominated oscillator independent of first order transistor speed dependency, wherein the RC dominated oscillator including one or more resistors and capacitors with programmable resistance and capacitance, and wherein the RC dominated oscillator to generate an output signal having a frequency depending substantially on values of the programmable resistance and capacitance; and a trim-able resistor or capacitor operable to be trimmed, for compensating process variations, according to a program code associated with the programmable resistance and capacitance of the RC dominated oscillator.
    Type: Application
    Filed: June 27, 2013
    Publication date: September 18, 2014
    Inventors: Fabrice PAILLET, Gerhard SCHROM, Alexander LYAKHOV, George L. GEANNOPOULOS, Ravi Sankar VUNNAM, J. Keith HODGSON