Patents by Inventor J. M. Drynan

J. M. Drynan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming DRAM circuitry
    Patent number: 6649466
    Abstract: In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: November 18, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Garo J. Derderian, M. R. Visokay, J. M. Drynan, Gurtej S. Sandhu
  • Method of forming DRAM circuitry
    Publication number: 20030017680
    Abstract: In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate.
    Type: Application
    Filed: September 13, 2002
    Publication date: January 23, 2003
    Inventors: Cem Basceri, Garo J. Derderian, M. R. Visokay, J. M. Drynan, Gurtej S. Sandhu
  • Method of depositing a tungsten comprising layer over a substrate, method of depositing an elemental tungsten comprising layer over a substrate, method of depositing a tungsten nitride comprising layer over a substrate, method of depositing a tungsten silicide comprising layer over a substrate, and method of forming a transistor gate line over a substrate
    Publication number: 20030013248
    Abstract: In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate.
    Type: Application
    Filed: September 13, 2002
    Publication date: January 16, 2003
    Inventors: Cem Basceri, Garo J. Derderian, M. R. Visokay, J. M. Drynan, Gurtej S. Sandhu
  • Method of forming a patterned substantially crystalline Ta2O5 comprising material, and method of forming a capacitor having a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material
    Publication number: 20030013277
    Abstract: In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate.
    Type: Application
    Filed: September 13, 2002
    Publication date: January 16, 2003
    Inventors: Cem Basceri, Garo J. Derderian, M. R. Visokay, J. M. Drynan, Gurtej S. Sandhu
  • Semiconductor processing method, method of forming DRAM circuitry, method of depositing a tungsten comprising layer over a substrate, method of forming a transistor gate line over a substrate, method of forming a patterned substantially crystalline Ta2O5 comprising material, and method of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material
    Publication number: 20020146894
    Abstract: In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate.
    Type: Application
    Filed: April 6, 2001
    Publication date: October 10, 2002
    Inventors: Cem Basceri, Garo J. Derderian, M. R. Visokay, J. M. Drynan, Gurtej S. Sandhu