Abstract: An axle assembly having an axle, a brake spider and a bearing collar. The axle may have first and second transition regions. The first transition region may extend between first and second cylindrical portions of the axle. The second transition region may extend between second and third cylindrical portions of the axle. The brake spider may be disposed on the second cylindrical portion. The bearing collar may be disposed on the second transition region.

Abstract: An axle assembly having an axle, a brake spider and a bearing collar. The axle may have first and second transition regions. The first transition region may extend between first and second cylindrical portions of the axle. The second transition region may extend between second and third cylindrical portions of the axle. The brake spider may be disposed on the second cylindrical portion. The bearing collar may be disposed on the second transition region.

Abstract: An electrically grounded semiconductor structure is embedded in a non-conductive packaging material, without employing any electrical leads of the semiconductor structure as an electrical path and without damaging the semiconductor structure. The desired grounding connection is obtained by physically removing a portion of the non-conductive packaging material from a rear portion of the semiconductor structure, replacing the removed non-conductive material by a conformable electrically conductive material, and then electrically contacting this conformable electrically conductive material to a grounding element. In another aspect of the invention, a portion of the non-conductive packaging material is removed from a rear portion of the semiconductor structure and a metallic element such as a pin or a spring is disposed to make contact between the exposed portion of the semiconductor structure and the grounding element.

Abstract: An asymmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes first and second main planar surfaces with the second main planar surface parallel to and positioned at a height lower that the first main planar surface. A third planar surface, generally normal to the first and second main planar surfaces, connects the first and second main planar surfaces on the drain region side of the channel region. The source region is formed in a portion of the first main planar surface, and the drain region is formed in the third planar surfaces and portions of the first and second main planar surfaces. Contours of equal ion concentration in the drain region are non-Gaussian and an interface between the channel region and drain region is generally linear beneath the gate electrode adjacent the generally normal third planar surface.

Abstract: An arched gate MOSFET having first and second source/drain regions formed spaced apart on a main surface of the semiconductor substrate, and a gate electrode formed on said main surface of the semiconductor substrate through an insulating film. The gate electrode extends in a first direction between the first and second source/drain regions defining a channel length, and in a second direction, perpendicular to the first direction, defining a channel width. The surface of the semiconductor substrate is arcuate in shape in the channel width direction and the gate electrode conforms to the arcuate shape of the surface of the semiconductor substrate.

Abstract: A symmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes a first region having a generally planar upper surface and a second region, projecting upwardly from the first region and having a generally planar upper surface, the second substrate region having opposed sidewalls generally normal to the upper surface of the first substrate region. A gate electrode is formed through an insulating film on the upper surface of the second substrate region, source/drain impurity regions are formed in the substrate on opposite sides of said gate electrode, and a channel region is formed under the gate electrode between the source/drain regions. Contours of equal ion concentration in the source/drain regions are non-Gaussian and an interface between the channel region and each source/drain region is generally linear beneath the gate electrode adjacent the opposing sidewalls of the second substrate region.