Abstract: Provided is a chemical injection system for connection to a chemical tank and a process line. The system includes a pump box configured to attach to the tank, the pump box including a body defining an interior, a pump assembly disposed within the interior of the body of the pump box, and an injection assembly configured to be fluidly coupled to the pump box. The injection assembly includes an injection lance having a flange and a stem, a first seal abutting a first side of the flange of the injection lance, and a second seal abutting a second side of the flange of the injection lance.

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

Abstract: A thin-film storage transistor in a NOR memory string has a gate dielectric layer that includes a silicon oxide nitride (SiON) tunnel dielectric layer. In one embodiment, the SiON tunnel dielectric layer has a thickness between 0.5 to 5.0 nm thick and an index of refraction between 1.5 and 1.9. The SiON tunnel dielectric layer may be deposited at between 720° C. and 900° C. and between 100 and 800 mTorr vapor pressure, using an LPCVD technique under DCS, N2O, and NH3 gas flows. The SiON tunnel dielectric layer may have a nitrogen content of 1-30 atomic percent (at %).

Abstract: A semiconductor memory device is implemented as strings of storage transistors, where the storage transistors in each string have drain terminals connected to a bit line and gate terminals connected to respective word lines. In some embodiments, the semiconductor memory device includes a reference bit line structure to provide a reference bit line signal for read operation. The reference bit line structure configures word line connections to provide a reference bit line to be used with a storage transistor being selected for read access. The reference bit line structure provides a reference bit line having the same electrical characteristics as an active bit line and is configured so that no storage transistors are selected when a word line is activated to access a selected storage transistor associated with the active bit line.

Abstract: Provided is a chemical injection system for connection to a chemical tank and a process line. The system includes a pump box configured to attach to the tank, the pump box including a body defining an interior, a pump assembly disposed within the interior of the body of the pump box, and an injection assembly configured to be fluidly coupled to the pump box. The injection assembly includes an injection lance having a flange and a stem, a first seal abutting a first side of the flange of the injection lance, and a second seal abutting a second side of the flange of the injection lance.

Abstract: A drug delivery investigation device includes a needle insertion mechanism having a cannula, a flow path having an inlet configured to be in fluid communication with a fluid source and an outlet, connection tubing extending between the outlet of the flow path and the needle insertion mechanism, with the connection tubing in fluid communication with the cannula and the flow path, a flow sensor positioned between the inlet and the outlet of the flow path, and a pressure sensor positioned between the inlet and the outlet of the flow path.

Abstract: A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.

Abstract: A memory structure includes randomly accessible, channel-all-around ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stacks are manufactured in a process that includes forming holes in a multi-layer film stack for forming local word line structures and slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structure of channel-all-around ferroelectric memory transistors enables a scalable construction for realizing a high density, high capacity memory device.

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

Abstract: Technology is disclosed for a current source for reading a memory cell having a threshold switching selector. The current source may be operated in a first mode when turning on the threshold switching selector and in a second mode when sensing a voltage across the memory cell. The first mode may allow the use of the full range of the power supply voltage, which provides sufficient voltage across the memory cell to turn on the threshold switching selector. In the second mode the magnitude of the read current is less dependent on the voltage across the memory cell. The second mode therefore provides for accurate sensing of the memory cell. The first mode may also be used when writing the memory cell, which provides sufficient voltage across the memory cell to write the memory cell.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory its, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: A drug delivery device includes a reservoir configured to receive a fluid, a cannula in fluid communication with the reservoir, with the cannula configured to be inserted into subcutaneous tissue or muscle tissue of a patient, and a pump configured to deliver a fluid from the reservoir to the cannula. The cannula includes a bioactive agent configured to cause a tissue response to decrease a pressure required to deliver fluid from the reservoir. The tissue response can include vasodilation, vasoconstriction, increased tissue permeability, increased flow of interstitial fluid or enzymatic deterioration of extracellular matrix.

Abstract: A semiconductor memory device implements a write disturb reduction method to reduce write disturb on unselected memory cells by alternating the order of the write logical “1” step and write logical “0” step in the write operations of selected memory cells associated with the same group of bit lines. In one embodiment, a method in an array of memory cells includes performing write operation on the memory cells in one of the memory pages to store write data into the memory cells where the write operation includes a first write step of writing a data of a first logical state and a second write step of writing data of a second logical state; and performing the write operation for each row of memory cells by alternately performing the first write step followed by the second write step and performing the second write step followed by the first write step.

Abstract: An extracorporeal blood disinfection system (10) includes an input tube (12) forming a flowpath (22) for infected blood from a mammalian patient (11); a disinfection unit (14) including a microbicidal light emitting device (24) emitting a plurality of light emissions, each light emission having a wavelength in a range between about 380 to about 800 nm; a treatment flowpath (22) in communication with the input tube (12) that is substantially transparent to emitted light of the microbicidal light emitting device (24) for receiving at least a portion of the infected blood flow therethrough, wherein the microbicidal light emitting device (24) effectuates a dose of light emissions to the infected blood in the treatment flowpath (22) to disinfect the blood; and an output tube (16) fluidly and physically connected wherein material can flow within the treatment flowpath forming a flowpath the disinfected blood flow from the disinfection unit to the patient.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: Provided is a chemical injection system for connection to a chemical tank and a process line. The system includes a pump box configured to attach to the tank, the pump box including a body defining an interior, a pump assembly disposed within the interior of the body of the pump box, and an injection assembly configured to be fluidly coupled to the pump box. The injection assembly includes an injection lance having a flange and a stem, a first seal abutting a first side of the flange of the injection lance, and a second seal abutting a second side of the flange of the injection lance.

Abstract: A chemical injection system for connection to a chemical tank and a process line includes a pump box configured to attach to the tank, the pump box including a body defining an interior, a pump assembly disposed within the interior of the body of the pump box, and an injection assembly configured to be fluidly coupled to the pump box. The injection assembly includes an injection lance having a flange and a stem, a first seal abutting a first side of the flange of the injection lance, and a second seal abutting a second side of the flange of the injection lance.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.