Patents by Inventor Jérôme JOIMEL
Jérôme JOIMEL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240169043Abstract: An electronic device includes a fingerprint sensor adapted to simultaneously acquiring fingerprints of a plurality of fingers, preferably from two to four fingers.Type: ApplicationFiled: March 15, 2022Publication date: May 23, 2024Inventors: Jean-Yves GOMEZ, Jérôme JOIMEL, Jérôme MICHALLON, Benjamin BOUTHINON
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Publication number: 20240152591Abstract: An electronic device adapted to executing at least one application, includes an access control, wherein a number of authentication means implemented by the access control is settable according to a security level assigned to the application.Type: ApplicationFiled: March 15, 2022Publication date: May 9, 2024Inventors: Jean-Yves GOMEZ, Jérôme JOIMEL, Jérôme MICHALLON, Benjamin BOUTHINON, Camille DUPOIRON
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Patent number: 11283046Abstract: An electronic device includes a substrate, a first oxygen- and water-tight protection layer covering the substrate, at least one electronic component located on the first protection layer and having at least one organic semiconductor region, an oxygen- and water-tight encapsulation layer, the oxygen- and water-tight encapsulation layer having an epoxy or acrylate glue totally covering the organic semiconductor region, a second oxygen- and water-tight protection layer totally covering the encapsulation layer, and a support layer covering the second oxygen- and water-tight protection layer.Type: GrantFiled: May 11, 2018Date of Patent: March 22, 2022Assignee: ISORGInventors: Jérôme Joimel, Eric Faupin
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Publication number: 20210233975Abstract: An optoelectronic device includes a display screen and an image sensor. The display screen includes a matrix of organic light-emitting components connected to first transistors and the image sensor includes a matrix of organic photodetectors connected to second transistors. The resolution of the optoelectronic device for the light-emitting components is greater than 300 ppi and the resolution of the optoelectronic device for the photodetectors is greater than 300 ppi. The total thickness of the optoelectronic device is less than 2 mm.Type: ApplicationFiled: June 3, 2019Publication date: July 29, 2021Inventors: Benjamin BOUTHINON, Emeline SARACCO, Jérôme JOIMEL
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Publication number: 20210159449Abstract: An electronic device includes a substrate, a first oxygen- and water-tight protection layer covering the substrate, at least one electronic component located on the first protection layer and having at least one organic semiconductor region, an oxygen- and water-tight encapsulation layer, the oxygen- and water-tight encapsulation layer having an epoxy or acrylate glue totally covering the organic semiconductor region, a second oxygen- and water-tight protection layer totally covering the encapsulation layer, and a support layer covering the second oxygen- and water-tight protection layer.Type: ApplicationFiled: May 11, 2018Publication date: May 27, 2021Inventors: Jérôme JOIMEL, Eric FAUPIN
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Patent number: 10957743Abstract: A matrix-array optoelectronic device includes a substrate on which a matrix array of what are called bottom electrodes is deposited; an active structure, which is preferably continuous and organic, arranged above the matrix-array of bottom electrodes, the structure being suitable for detecting light; and at least one what is called top electrode lying above the active structure, the top electrode being transparent to the light emitted or detected by the active structure; and at least one conductive element that is borne by the substrate without interposition of the active structure and that is connected to the top electrode by at least one vertical interconnection, the conductive element having an electrical conductivity greater than that of the top electrode. The device may also comprise a layer made of scintillator material, the layer being fastened to the top electrode, so as to form an x-ray imager.Type: GrantFiled: December 19, 2016Date of Patent: March 23, 2021Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, ISORG, TRIXELLInventors: Mohammed Benwadih, Jean-Marie Verilhac, Simon Charlot, Jérôme Joimel, Pierre Rohr
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Publication number: 20190013361Abstract: A matrix-array optoelectronic device includes a substrate on which a matrix array of what are called bottom electrodes is deposited; an active structure, which is preferably continuous and organic, arranged above the matrix-array of bottom electrodes, the structure being suitable for detecting light; and at least one what is called top electrode lying above the active structure, the top electrode being transparent to the light emitted or detected by the active structure; and at least one conductive element that is borne by the substrate without interposition of the active structure and that is connected to the top electrode by at least one vertical interconnection, the conductive element having an electrical conductivity greater than that of the top electrode. The device may also comprise a layer made of scintillator material, the layer being fastened to the top electrode, so as to form an x-ray imager.Type: ApplicationFiled: December 19, 2016Publication date: January 10, 2019Inventors: Mohammed BENWADIH, Jean-Marie VERILHAC, Simon CHARLOT, Jérôme JOIMEL, Pierre ROHR
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Patent number: 9466510Abstract: A technique comprising: mounting a device substrate on a processing support, forming one or more electronic elements on the device substrate with the device substrate thus mounted on the processing support; wherein the device substrate comprises an organic support structure, and provides primary protection for the overlying electronic elements against the ingress of a degrading species from a side of the device substrate opposite to the one or more electronic elements.Type: GrantFiled: June 3, 2011Date of Patent: October 11, 2016Assignee: FLEXENABLE LIMITEDInventors: Kieran Reynolds, Jerome Joimel
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Patent number: 9130179Abstract: A device comprising an array of transistors, including: patterned conductive layers located at lower and upper levels in a stack of layers on a substrate, which patterned conductive layers define gate conductors and source-drain electrodes of the array of transistors; wherein the stack of layers further comprises a dielectric layer below said lower level, and a further patterned conductive layer below said dielectric layer; and wherein said further patterned conductive layer both provides an electrical function in said array of transistors via said dielectric layer, and defines openings via which the dielectric layer serves to increase the strength of adhesion between the device substrate and the patterned conductive layer at said lower level.Type: GrantFiled: November 25, 2011Date of Patent: September 8, 2015Assignee: PLASTIC LOGIC LIMITEDInventors: Martin Jackson, Catherine Ramsdale, Jerome Joimel
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Publication number: 20130299815Abstract: A device comprising an array of transistors, including: patterned conductive layers located at lower and upper levels in a stack of layers on a substrate, which patterned conductive layers define gate conductors and source-drain electrodes of the array of transistors; wherein the stack of layers further comprises a dielectric layer below said lower level, and a further patterned conductive layer below said dielectric layer; and wherein said further patterned conductive layer both provides an electrical function in said array of transistors via said dielectric layer, and defines openings via which the dielectric layer serves to increase the strength of adhesion between the device substrate and the patterned conductive layer at said lower level.Type: ApplicationFiled: November 25, 2011Publication date: November 14, 2013Applicant: PLASTIC LOGIC LIMITEDInventors: Martin Jackson, Catherine Ramsdale, Jerome Joimel
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Publication number: 20130143362Abstract: A technique comprising: mounting a device substrate on a processing support, forming one or more electronic elements on the device substrate with the device substrate thus mounted on the processing support; wherein the device substrate comprises an organic support structure, and provides primary protection for the overlying electronic elements against the ingress of a degrading species from a side of the device substrate opposite to the one or more electronic elements.Type: ApplicationFiled: June 3, 2011Publication date: June 6, 2013Applicant: PLASTIC LOGIC LIMITEDInventors: Kieran Reynolds, Jerome Joimel
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Publication number: 20120193721Abstract: Forming, between a supporting substrate and the bottom conductive layer of a stack of layers a plurality of electronically functional elements, a non-conducting layer that functions to increase the adhesion of said bottom conductive layer to the supporting substrate.Type: ApplicationFiled: June 4, 2010Publication date: August 2, 2012Applicant: PLASTIC LOGIC LIMITEDInventors: Jerome Joimel, Catherine Ramsdale, Frank Placido
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Publication number: 20110223095Abstract: An apparatus includes a substrate and a carbon nanotube film on the substrate. The carbon nanotube film includes microscopically visible overlapping dots of carbon nanotubes. The overlapping dots being microscopically visible signifies that the carbon nanotube film was formed by depositing a solution of the carbon nanotubes on the substrate in a single pass manner.Type: ApplicationFiled: December 18, 2008Publication date: September 15, 2011Inventors: Elizabeth Harvey, Jerome Joimel, Anna Fenelon