Patents by Inventor Jérôme Lacan
Jérôme Lacan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103965Abstract: A method for managing the consumption of a memory device includes performing a first reading of data in a first portion of a first memory area of the memory device. During a same memory access, error correction code check bits are read from a second portion of a second memory area of the memory device. The error correction check bits include error correction check bits that are associated with the data in the first portion of the first memory area and other error correction code check bits associated with other data. All of the other error correction code check bits are stored in a register, and the other data in the first portion of the first memory area is read. The error correction code bits associated with the other data are extracted from the register.Type: ApplicationFiled: August 31, 2023Publication date: March 28, 2024Inventors: Laura Martinez, Jerome Lacan
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Publication number: 20230085493Abstract: A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.Type: ApplicationFiled: September 12, 2022Publication date: March 16, 2023Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics Design and Application S.R.O.Inventors: Jerome LACAN, Remi COLLETTE, Christophe EVA, Milan KOMAREK
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Patent number: 11304241Abstract: A method for transmitting data packets through a random-access (RA) transmission channel shared by a plurality of user terminals uses and exploits a function F for assigning and distributing transmission resources F(u) to the user terminals, knowledge of the graph of which is shared by the sending user terminals and the receiving station in a preliminary step. During the decoding of the received packets, the graph {(u, F(u)} of the assigning and distributing function is exploited by the receiving station to minimize, or even to decrease to zero, the number of replica-location correlations required in case of failure of the conventional CRD-SA protocol decoding process.Type: GrantFiled: May 2, 2019Date of Patent: April 12, 2022Assignees: THALES, CENTRE NATIONAL D'ETUDES SPATIALES PARIS, FRANCE, INSTITUT SUPERIEUR DE L'AERONAUTIQUE ET DE L'ESPACE TOULOUSE, FRANCE, INSTITUT NATIONAL POLYTECHNIQUE DE TOULOUSE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Selma Zamoum, Mathieu Gineste, Jérôme Lacan, Marie-Laure Boucheret, Jean-Baptiste Dupe
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Publication number: 20210368552Abstract: A method for transmitting data packets through a random-access (RA) transmission channel shared by a plurality of user terminals uses and exploits a function F for assigning and distributing transmission resources F(u) to the user terminals, knowledge of the graph of which is shared by the sending user terminals and the receiving station in a preliminary step. During the decoding of the received packets, the graph {(u, F(u)} of the assigning and distributing function is exploited by the receiving station to minimize, or even to decrease to zero, the number of replica-location correlations required in case of failure of the conventional CRD-SA protocol decoding process.Type: ApplicationFiled: May 2, 2019Publication date: November 25, 2021Inventors: Selma ZAMOUM, Mathieu GINESTE, Jérôme LACAN, Marie-Laure BOUCHERET, Jean-Baptiste DUPE
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Publication number: 20170201271Abstract: A process of encoding information data in a sequence of bursts ( . . . , Bi-2, Bi-1 Bi, Bi+1, . . . ), each burst comprising a block of information symbols and a block of redundancy symbols. The block of redundancy symbols (R,) of the current burst (B,) of the sequence is generated by calculating a sum of a series of coding values relating to a series of bursts (Bi-2, Bi-1), each coding value of the series of coding values being obtained by a respective coding function applied to the block of information symbols of the corresponding burst of the series of bursts.Type: ApplicationFiled: October 6, 2015Publication date: July 13, 2017Inventors: Guillaume Smith, Jerome LACAN, Laurence CLARAC
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Publication number: 20170099067Abstract: A process of encoding information data in a sequence of bursts ( . . . , Bi-2, Bi-1 Bi, Bi+1, . . . ), each burst comprising a block of information symbols and a block of redundancy symbols. The block of redundancy symbols (R,) of the current burst (B,) of the sequence is generated by calculating a sum of a series of coding values relating to a series of bursts (Bi-2, Bi-1), each coding value of the series of coding values being obtained by a respective coding function applied to the block of information symbols of the corresponding burst of the series of bursts.Type: ApplicationFiled: October 6, 2015Publication date: April 6, 2017Inventors: Guillaume Smith, Jerome LACAN, Laurence CLARAC
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Patent number: 9281848Abstract: A process of encoding information data in a sequence of bursts ( . . . , Bi?2, Bi?1, Bi, Bi+1, . . . ), each burst comprising a block of information symbols and a block of redundancy symbols. The block of redundancy symbols (Ri) of the current burst (Bi) of the sequence is generated by calculating a sum of a series of coding values relating to a series of bursts (Bi?2, Bi?1), each coding value of the series of coding values being obtained by a respective coding function applied to the block of information symbols of the corresponding burst of the series of bursts.Type: GrantFiled: June 21, 2012Date of Patent: March 8, 2016Assignee: CENTRE NATIONAL D'ETUDES SPATIALESInventors: Guillaume Smith, Jerome Lacan, Laurence Clarac
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Publication number: 20140136923Abstract: A process of encoding information data in a sequence of bursts ( . . . , Bi?2, Bi?1, Bi, Bi+1, . . . ), each burst comprising a block of information symbols and a block of redundancy symbols. The block of redundancy symbols (Ri) of the current burst (Bi) of the sequence is generated by calculating a sum of a series of coding values relating to a series of bursts (Bi?2, Bi?1), each coding value of the series of coding values being obtained by a respective coding function applied to the block of information symbols of the corresponding burst of the series of bursts.Type: ApplicationFiled: June 21, 2012Publication date: May 15, 2014Applicant: CENTRE NATIONAL D'ETUDES SPATIALESInventors: Guillaume Smith, Jerome Lacan, Laurence Clarac
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Patent number: 8677033Abstract: Embodiments described in the present disclosure relate to a method for initializing registers of peripherals of a microcontroller, including acts of: accessing initialization data in a non-volatile memory connected by a main bus to a processing unit of the microcontroller and to the peripherals, activating a peripheral including registers to be initialized, and transferring the data read into the registers of the activated peripheral, the initialization data being accessed in the memory by an initialization circuit distinct from the processing unit, the initialization data accessed being sent to the peripherals by an initialization bus distinct from the main bus.Type: GrantFiled: July 3, 2012Date of Patent: March 18, 2014Assignee: STMicroelectronics (Rousset) SASInventors: Jerome Lacan, Sandrine Lendre
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Patent number: 8582600Abstract: A method for delineating a data stream transmitted by a communication system using a protocol stack includes: analyzing the redundancy of sequences, the content of which is set on one or more layers in a protocol stack to delineate packets, errored or not, in a continuous data stream; the method to this end including searching in the receiver for sequences corresponding to a known sequence SP present in the received stream, and doing so by detecting sequences similar to this known sequence, the non-similar sequences not being retained; the method further including, in the presence of similar sequences, storing their position to determine the start of the packets.Type: GrantFiled: February 20, 2009Date of Patent: November 12, 2013Assignee: ThalesInventors: Juan Cantillo, Jérôme Lacan, Isabelle Buret, Fabrice Arnal
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Patent number: 8479074Abstract: The subject of the present invention is a method for correcting transmission errors in a data stream transmitted by a communications system using a protocol stack. According to the invention, the method consists in utilizing the redundancy of sequences whose content is fixed across several layers in a stack of protocols so as to correct transmission errors; the method consisting to this end in searching at the level of the receiver for sequences corresponding to a known sequence present in the stream received and doing so by detecting sequences similar to this known sequence, non-similar sequences not being retained; the method consisting furthermore, when similar sequences are present, in detecting transmission errors in the known sequence and in modifying the similar sequences (erroneous sequences) with the aid of the known sequence.Type: GrantFiled: December 2, 2008Date of Patent: July 2, 2013Assignee: ThalesInventors: Juan Cantillo, Jérôme Lacan, Isabelle Buret, Fabrice Arnal
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Publication number: 20130013820Abstract: Embodiments described in the present disclosure relate to a method for initializing registers of peripherals of a microcontroller, including acts of: accessing initialization data in a non-volatile memory connected by a main bus to a processing unit of the microcontroller and to the peripherals, activating a peripheral including registers to be initialized, and transferring the data read into the registers of the activated peripheral, the initialization data being accessed in the memory by an initialization circuit distinct from the processing unit, the initialization data accessed being sent to the peripherals by an initialization bus distinct from the main bus.Type: ApplicationFiled: July 3, 2012Publication date: January 10, 2013Applicant: STMICROELECTRONICS (ROUSSET) SASInventors: Jerome Lacan, Sandrine Lendre
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Publication number: 20110317547Abstract: A method for robustly transmitting a data flow in the form of packets Pi including at least one header Hi, said header being compressed via a first header compression step, said packets being fragmented into a succession of cells, said cells having an identical fixed size, said fragmentation resulting in the appearance of a padding section in the last of said cells, where the space occupied by said padding section is used, at least partially, to insert redundancy data, the function of said redundancy data being to increase the robustness to transmission errors of said compressed header.Type: ApplicationFiled: March 4, 2010Publication date: December 29, 2011Applicant: THALESInventors: Cédric Baudoin, Fabrice Arnal, Jérôme Lacan
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Publication number: 20110032949Abstract: A method for delineating a data stream transmitted by a communication system using a protocol stack includes: analyzing the redundancy of sequences, the content of which is set on one or more layers in a protocol stack to delineate packets, errored or not, in a continuous data stream; the method to this end including searching in the receiver for sequences corresponding to a known sequence SP present in the received stream, and doing so by detecting sequences similar to this known sequence, the non-similar sequences not being retained; the method further including, in the presence of similar sequences, storing their position to determine the start of the packets.Type: ApplicationFiled: February 20, 2009Publication date: February 10, 2011Applicant: THALESInventors: Juan Cantillo, Jerome Lacan, Isabelle Buret, Fabrice Arnal
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Publication number: 20100318882Abstract: The subject of the present invention is a method for correcting transmission errors in a data stream transmitted by a communications system using a protocol stack. According to the invention, the method consists in utilizing the redundancy of sequences whose content is fixed across several layers in a stack of protocols so as to correct transmission errors; the method consisting to this end in searching at the level of the receiver for sequences corresponding to a known sequence present in the stream received and doing so by detecting sequences similar to this known sequence, non-similar sequences not being retained; the method consisting furthermore, when similar sequences are present, in detecting transmission errors in the known sequence and in modifying the similar sequences (erroneous sequences) with the aid of the known sequence.Type: ApplicationFiled: December 2, 2008Publication date: December 16, 2010Applicant: THALESInventors: Juan Cantillo, Jerome Lacan, Isabelle Buret, Fabrice Arnal
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Patent number: 7194644Abstract: The present invention relates to an integrated circuit comprising a central processing unit clocked by a clock signal, a main oscillator circuit supplying a first clock signal and a peripheral circuit supplying a periodic wake up signal, the central processing unit comprising a first operating mode at full power, in which the first clock signal is applied to the central processing unit, and an active halt mode in which the main oscillator circuit and the central processing unit are deactivated, the central processing unit being awakened by the periodic wake-up signal.Type: GrantFiled: February 6, 2004Date of Patent: March 20, 2007Assignee: STMicroelectronics S.A.Inventors: Benoît Durand, Jérôme Lacan
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Publication number: 20040221187Abstract: The present invention relates to an integrated circuit comprising a central processing unit clocked by a clock signal, a main oscillator circuit supplying a first clock signal and a peripheral circuit supplying a periodic wake up signal, the central processing unit comprising a first operating mode at full power, in which the first clock signal is applied to the central processing unit, and an active halt mode in which the main oscillator circuit and the central processing unit are deactivated, the central processing unit being awakened by the periodic wake-up signal.Type: ApplicationFiled: February 6, 2004Publication date: November 4, 2004Applicant: STMicroelectronics S.A.Inventors: Benoit Durand, Jerome Lacan