Patents by Inventor Jérôme Laurent

Jérôme Laurent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240093305
    Abstract: The invention relates to an in vitro method for detecting or monitoring an endometrial or ovarian carcinoma in a human subject, which method comprises detecting, or determining the level of, methylation of OXT and/or ZSCAN12 gene in a biological sample from the subject.
    Type: Application
    Filed: January 24, 2022
    Publication date: March 21, 2024
    Inventors: Jérôme Alexandre, Bruno Borghese, Guillaume Beinse, Valérie Taly, Pierre Laurent-Puig, Pierre-Alexandre Just
  • Publication number: 20230386762
    Abstract: The present application concerns a circuit breaker including a movable contact, a driving rod slidably mounted in the circuit breaker, a linkage mechanism for driving the movable contact, a pivoted driving fork rotatably mounted in the circuit breaker which cooperates with the driving rod through the cooperation of a primary pin provided on the driving rod and a primary slot provided on the driving fork, a driven lever connecting the driving fork to the movable contact, and wherein the driving rod supports a secondary pin which cooperates with a secondary slot of the driving fork when the driving rod in a position between a predetermined position and an extreme opened position of the circuit breaker.
    Type: Application
    Filed: October 18, 2021
    Publication date: November 30, 2023
    Applicant: General Electric Technology GmbH
    Inventors: David BERARD, Quentin, Dominique, Louis ROGNARD, Jérôme LAURENT, Serge BACHELARD
  • Publication number: 20230386771
    Abstract: The present application concerns a high-voltage circuit breaker filled with insulating gas having a main axis A, including arcing contacts and an insulating nozzle, wherein an insulating gas flowing from a storage chamber and heated by an electric arc between the two arcing contacts is partitioned into a first gas flow and a second gas flow conducted outside of the insulating nozzle from opposite directions toward a main gas chamber, wherein the first gas flow flows through a first intermediary gas chamber and the second gas flow flows through a second intermediary gas chamber and is partitioned in a first portion directed to the main gas chamber and a second portion directed to an exhaust gas chamber, characterized in that the first portion of the second gas flow is smaller than the second portion of the second gas flow.
    Type: Application
    Filed: October 12, 2021
    Publication date: November 30, 2023
    Applicant: General Electric Technology GmbH
    Inventors: Quentin, Dominique, Louis ROGNARD, David BERARD, Cyril GREGOIRE, Jérôme LAURENT
  • Publication number: 20230005675
    Abstract: The invention concerns a double-motion circuit breaker comprising primary and secondary movable contacts slidingly mounted within primary and secondary holders, wherein the primary movable contact comprises a tulip and a contact cylinder attached thereto, and the secondary movable contact comprises a pin for engaging the tulip but no counter-contact for engaging the contact cylinder. The circuit breaker also has a non-linear linkage mechanism with a pin and slot mechanism, and a fixed dielectric shield provided on the secondary holder. During disconnection, the linkage mechanism is preferably arranged to move the pin more than the tulip, proportionally to their maximum stroke, so as to quickly bring the pin tip within the fixed dielectric shield, whereafter the tulip moves more than the pin. This circuit breaker is cheaper, lighter and can be disconnected more quickly.
    Type: Application
    Filed: November 26, 2020
    Publication date: January 5, 2023
    Applicant: General Electric Technology GmbH
    Inventors: Quentin ROGNARD, Jerome LAURENT, David BERARD
  • Publication number: 20220347754
    Abstract: Controlled manufacturing system suitable for controlling a method for manufacturing, repairing or resurfacing a part by deposition of material under concentrated energy, said controlled manufacturing system comprising: means for obtaining a three-dimensional digital model of the part; means for generating a manufacturing file for the part, based on the three-dimensional digital model of said part, to define manufacturing parameters of an additive manufacturing machine, said manufacturing parameters being associated with manufacturing instructions; means for generating a control file for the part to define control parameters of a control effector, said control parameters being associated with control instructions; analysis means for carrying out an analysis of the manufacturing file and the control file in order to determine if the manufacturing parameters and the control parameters can coexist during the simultaneous application of the manufacturing parameters to the additive manufacturing machine and the
    Type: Application
    Filed: May 25, 2020
    Publication date: November 3, 2022
    Inventors: JEAN-DANIEL PENOT, JEROME LAURENT, CELIA MILLON, PHILIPPE VERLET, JONATHAN FRECHARD
  • Patent number: 11127550
    Abstract: A contact arrangement for a Pre-Insertion Resistor (PIR) wherein a control rod is arranged to move a movable contact, against the force of a biasing member, into temporary connection with a PIR. The control rod comprises a tulip with a plurality of resilient fingers and having a first diameter where it is able to mechanically couple to a latching ring on the movable contact, and a second diameter where the tulip is deformed with the fingers deflected inwards, once the resistance to movement exceeds a predetermined value, wherein the latching ring is able to pass over the tulip to decouple the movable contact from the control rod. The contact arrangement is particularly suited for a PIR arranged for connection in parallel to the interrupter of a gas-insulated switchgear (GIS) circuit breaker.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 21, 2021
    Assignee: General Electric Technology GmbH
    Inventors: Keith McLaughlin, Ludovic Darles, Jérôme Laurent, Thomas Tometich, Andrew Chovanec, Chase Peltier
  • Patent number: 11085900
    Abstract: A method for nondestructively testing a part comprising an elongate microstructure is disclosed.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: August 10, 2021
    Assignees: SAFRAN, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, ECOLE SUPERIEURE DE PHYSIQUE ET DE CHIMIE, INDUSTRIELLES DE LA VILLE DE PARIS
    Inventors: Aurélien Baelde, Frédéric Jenson, Mathias Fink, Jérôme Laurent, Claire Prada
  • Publication number: 20210141871
    Abstract: A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 13, 2021
    Inventors: Gregory Remy Philippe Conti, Jerome Laurent Azema
  • Patent number: 10902092
    Abstract: A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: January 26, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Remy Philippe Conti, Jerome Laurent Azema
  • Publication number: 20200388454
    Abstract: The invention concerns a contact arrangement (50) for a Pre-Insertion Resistor (PIR) wherein a control rod (20) is arranged to move a movable contact (30), against the force of a biasing member (18), into temporary connection with a PIR. The control rod (20) comprises a tulip (21) with a plurality of resilient fingers (24) and having a first diameter where it is able to mechanically couple to a latching ring (31) on the movable contact (30), and a second diameter where the tulip (21) is deformed with the fingers (24) deflected inwards, once the resistance to movement exceeds a predetermined value, wherein the latching ring (31) is able to pass over the tulip (21) to decouple the movable contact (30) from the control rod (20). The contact arrangement (50) is particularly suited for a PIR arranged for connection in parallel to the interrupter of a gas-insulated switchgear (GIS) circuit breaker.
    Type: Application
    Filed: June 4, 2020
    Publication date: December 10, 2020
    Inventors: Keith MCLAUGHLIN, Ludovic DARLES, Jérôme LAURENT, Thomas TOMETICH, Andrew CHOVANEC, Chase PELTIER
  • Publication number: 20190360969
    Abstract: A method for nondestructively testing a part comprising an elongate microstructure is disclosed.
    Type: Application
    Filed: January 23, 2018
    Publication date: November 28, 2019
    Applicants: SAFRAN, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, ECOLE SUPERIEURE DE PHYSIQUE ET DE CHIMIE INDUSTRIELLES DE LA VILLE DE PARIS
    Inventors: Aurélien Baelde, Frédéric Jenson, Mathias Fink, Jérôme Laurent, Claire Prada
  • Publication number: 20190349420
    Abstract: An electronic device includes: a processor; and a memory coupled to the processor, wherein the memory stores instructions that, when executed by the processor, cause the processor to: transmit a request, from a first module to a first external cloud, to receive data regarding a first electronic device in communication with the first external cloud; receive the data regarding the first electronic device from the first external cloud; store, in the memory, the data regarding the first electronic device as part of a representation of the first electronic device; receive data regarding a second electronic device from a second external cloud; and transmit a signal to the first external cloud in response to receiving the data regarding the second electronic device for controlling an operation of the first electronic device.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 14, 2019
    Inventors: Luc Julia, Gilles Mazars, Jerome Laurent Dubreuil
  • Patent number: 10334024
    Abstract: An electronic device includes: a processor; and a memory coupled to the processor, wherein the memory stores instructions that, when executed by the processor, cause the processor to: transmit a request, from a first module to a first external cloud, to receive data regarding a first electronic device in communication with the first external cloud; receive the data regarding the first electronic device from the first external cloud; store, in the memory, the data regarding the first electronic device as part of a representation of the first electronic device; receive data regarding a second electronic device from a second external cloud; and transmit a signal to the first external cloud in response to receiving the data regarding the second electronic device for controlling an operation of the first electronic device.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Luc Julia, Gilles Mazars, Jerome Laurent Dubreuil
  • Patent number: 10250590
    Abstract: A method of secure device registration is presented. The method comprises: receiving a registration request from a device; validating the device on the basis of the registration request; in response to successfully validating the device, sending a passcode to the device via a first connection; prompting a user for the passcode via a second connection different from the first connection; receiving the passcode via the second connection; and sending an authorization token to the device via the first connection.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 2, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Oleg Gryb, Jerome Laurent Dubreuil, Luc Julia
  • Publication number: 20170208118
    Abstract: An electronic device includes: a processor; and a memory coupled to the processor, wherein the memory stores instructions that, when executed by the processor, cause the processor to: transmit a request, from a first module to a first external cloud, to receive data regarding a first electronic device in communication with the first external cloud; receive the data regarding the first electronic device from the first external cloud; store, in the memory, the data regarding the first electronic device as part of a representation of the first electronic device; receive data regarding a second electronic device from a second external cloud; and transmit a signal to the first external cloud in response to receiving the data regarding the second electronic device for controlling an operation of the first electronic device.
    Type: Application
    Filed: May 20, 2016
    Publication date: July 20, 2017
    Inventors: Julia Luc, Gilles Mazars, Jerome Laurent Dubreuil
  • Publication number: 20170063834
    Abstract: A method of secure device registration is presented. The method comprises: receiving a registration request from a device; validating the device on the basis of the registration request; in response to successfully validating the device, sending a passcode to the device via a first connection; prompting a user for the passcode via a second connection different from the first connection; receiving the passcode via the second connection; and sending an authorization token to the device via the first connection.
    Type: Application
    Filed: December 30, 2015
    Publication date: March 2, 2017
    Inventors: Oleg GRYB, Jerome Laurent DUBREUIL, Luc JULIA
  • Publication number: 20150178513
    Abstract: A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.
    Type: Application
    Filed: January 13, 2015
    Publication date: June 25, 2015
    Inventors: Gregory Remy Philippe Conti, JEROME LAURENT AZEMA
  • Patent number: 9063889
    Abstract: A computing system comprising a processor having a first and second bus (the processor on a first semiconductor die mounted within a semiconductor package), a monitoring device coupled to both the first and second bus of the processor (the monitoring device on the first semiconductor die mounted within the semiconductor package), a memory coupled to the processor via the first bus (coupled to the monitoring device via a security signal, the memory on a second semiconductor die mounted within the semiconductor package), and a user interface external of the semiconductor package (the user interface coupled to the processor via the second data and instruction bus). The monitoring device checks one or both of the first and second busses to determine whether a secure mode entry sequence is delivered to the processor. The first bus and the security signal are only coupled to and accessible by devices within the semiconductor package.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: June 23, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gregory Remy Philippe Conti, Jerome Laurent Azema, Jerome Neanne
  • Patent number: 8966226
    Abstract: A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: February 24, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Remy Philippe Conti, Jerome Laurent Azema
  • Publication number: 20120278880
    Abstract: A system is provided that includes a processor and a system memory coupled to the processor, the system memory stores at least one application for execution by the processor. The system also includes logic coupled to the processor, the logic providing a secure time reference. The processor selectively accesses the secure time reference to generate a virtual time reference for the at least one application.
    Type: Application
    Filed: July 9, 2012
    Publication date: November 1, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Guillaume Leterrier, Jerome Laurent Azema