Patents by Inventor J. Randall Creighton

J. Randall Creighton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7745315
    Abstract: A method for forming vertically oriented, crystallographically aligned nanowires (nanocolumns) using monolayer or submonolayer quantities of metal atoms to form uniformly sized metal islands that serve as catalysts for MOCVD growth of Group III nitride nanowires.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: June 29, 2010
    Assignee: Sandia Corporation
    Inventors: George T. Wang, Qiming Li, J. Randall Creighton
  • Patent number: 7670933
    Abstract: A method for growing high quality, nonpolar Group III nitrides using lateral growth from Group III nitride nanowires. The method of nanowire-templated lateral epitaxial growth (NTLEG) employs crystallographically aligned, substantially vertical Group III nitride nanowire arrays grown by metal-catalyzed metal-organic chemical vapor deposition (MOCVD) as templates for the lateral growth and coalescence of virtually crack-free Group III nitride films. This method requires no patterning or separate nitride growth step.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: March 2, 2010
    Assignee: Sandia Corporation
    Inventors: George T. Wang, Qiming Li, J. Randall Creighton
  • Patent number: 7449404
    Abstract: A method for improving Mg doping of Group III-N materials grown by MOCVD preventing condensation in the gas phase or on reactor surfaces of adducts of magnesocene and ammonia by suitably heating reactor surfaces between the location of mixing of the magnesocene and ammonia reactants and the Group III-nitride surface whereon growth is to occur.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: November 11, 2008
    Assignee: Sandia Corporation
    Inventors: J. Randall Creighton, George T. Wang
  • Patent number: 5663098
    Abstract: A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: September 2, 1997
    Assignee: Sandia Corporation
    Inventors: J. Randall Creighton, Frank Dominguez, A. Wayne Johnson, Thomas R. Omstead