Abstract: An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

Abstract: An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

Abstract: Logic basic cell and logic basic cell arrangement having a plurality of logic basic cells. A logic basic cell includes at least six data signal inputs, a first logic function block and a second logic function block, at least one logic function configuration input, a first multiplexer and a second multiplexer.

Abstract: A logic basic cell contains a first logic function block and a second logic function block for the logic combination of a first input signal and a second input signal in accordance with a predeterminable first or second logic subfunction, and a first logic transistor coupled to the first logic function block, having a gate terminal, at which a third input signal can be provided, and having a source/drain terminal at which the output signal can be provided. Furthermore, a second logic transistor coupled to the second logic function block is provided, having a gate terminal, at which a complementary signal with respect to the third input signal can be provided, and having a source/drain terminal, which is coupled to the source/drain terminal of the first logic transistor.

Abstract: A logic basic cell, a logic basic cell arrangement, and a logic device. A logic basic cell is provided for forming a logic combination of two data signals in accordance with a logic function that can be selected by means of a plurality of logic selection elements, having four data signal inputs, to which two data signals and the logically complementary data signals thereof can be applied, and having six logic selection elements between the data signal inputs. At a data signal output, the logic combination of the two data signals in accordance with the logic function selected by means of the logic selection elements can be provided as output signal.

Abstract: A logic circuit arrangement including at least two data signal inputs, at which at least two data signals are provided, a first signal path coupled to the data signal inputs, and having a plurality of transistors of a first conduction type, and a plurality of control inputs coupled to the transistors.