Patents by Inventor Jörg Siegert

Jörg Siegert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11946822
    Abstract: In an embodiment a semiconductor transducer device includes a semiconductor body and a diaphragm having a first layer and a second layer, wherein a main extension plane of the diaphragm is arranged parallel to a surface of the semiconductor body, wherein the diaphragm is suspended at a distance from the semiconductor body in a direction perpendicular to the main extension plane of the diaphragm, wherein the second layer comprises titanium and/or titanium nitride, wherein the first layer comprises a material that is resistant to an etchant comprising fluorine or a fluorine compound, and wherein the second layer is arranged between the semiconductor body and the first layer.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: April 2, 2024
    Assignee: Sciosense B.V.
    Inventors: Alessandro Faes, Jörg Siegert, Willem Frederik Adrianus Besling, Remco Henricus Wilhelmus Pijnenburg
  • Patent number: 11878906
    Abstract: In an embodiment, an integrated MEMS transducer device includes a substrate body having a first electrode on a substrate, an etch stop layer located on a surface of the substrate, a suspended micro-electro-mechanical systems (MEMS) diaphragm with a second electrode, an anchor structure with anchors connecting the MEMS diaphragm to the substrate body and a sacrificial layer in between the anchors of the anchor structure, the sacrificial layer including a first sub-layer of a first material, wherein the first sub-layer is arranged on the etch stop layer, a second sub-layer of a second material, wherein the second sub-layer is arranged on the first sub-layer, and wherein the first and the second material are different materials.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: January 23, 2024
    Assignee: Sciosense B.V.
    Inventors: Kailash Vijayakumar, Remco Henricus Wilhelmus Pijnenburg, Willem Frederik Adrianus Besling, Sophie Guillemin, Jörg Siegert
  • Patent number: 11764109
    Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 19, 2023
    Assignee: AMS AG
    Inventors: Jochen Kraft, Georg Parteder, Stefan Jessenig, Franz Schrank, Jörg Siegert
  • Patent number: 11697201
    Abstract: An exoskeleton system includes a first exoskeleton unit configured to support a first body part, a second exoskeleton unit configured to support a second body part, and a control device. The first exoskeleton unit and the second exoskeleton unit are mechanically decoupled from each other. The control device is configured to control, based on a control model, at least one of the first exoskeleton unit and the second exoskeleton unit. The control model is based on a multibody system that models the first exoskeleton unit, the second exoskeleton unit, and at least one of the first body part and the second body part.
    Type: Grant
    Filed: May 9, 2020
    Date of Patent: July 11, 2023
    Assignee: Universitaet Stuttgart
    Inventors: Joerg Siegert, Urs Schneider
  • Patent number: 11585711
    Abstract: A capacitive sensor is disclosed. In an embodiment a semiconductor device includes a die including a capacitive pressure sensor integrated on a CMOS circuit, wherein the capacitive pressure sensor includes a first electrode and a second electrode separated from one another by a cavity, the second electrode including a suspended tensile membrane, and wherein the first electrode is composed of one or more aluminum-free layers containing Ti.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: February 21, 2023
    Assignee: SCIOSENSE B.V.
    Inventors: Willem Frederik Adrianus Besling, Remco Henricus Wilhelmus Pijnenburg, Kailash Vijayakumar, Jörg Siegert, Alessandro Faes
  • Patent number: 11572271
    Abstract: The disclosure relates to a method for manufacturing a planarized etch-stop layer, ESL, for a hydrofluoric acid, HF, vapor phase etching process. The method includes providing a first planarized layer on top of a surface of a substrate, the first planarized layer having a patterned and structured metallic material and a filling material. The method further includes depositing on top of the first planarized layer the planarized ESL of an ESL material with low HF etch rate, wherein the planarized ESL has a low surface roughness and a thickness of less than 150 nm, in particular of less than 100 nm.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: February 7, 2023
    Assignee: AMS AG
    Inventors: Alessandro Faes, Sophie Guillemin, Joerg Siegert, Karl Tuttner
  • Publication number: 20230036935
    Abstract: In an embodiment, an integrated MEMS transducer device includes a substrate body having a first electrode on a substrate, an etch stop layer located on a surface of the substrate, a suspended micro-electro-mechanical systems (MEMS) diaphragm with a second electrode, an anchor structure with anchors connecting the MEMS diaphragm to the substrate body and a sacrificial layer in between the anchors of the anchor structure, the sacrificial layer including a first sub-layer of a first material, wherein the first sub-layer is arranged on the etch stop layer, a second sub-layer of a second material, wherein the second sub-layer is arranged on the first sub-layer, and wherein the first and the second material are different materials.
    Type: Application
    Filed: September 30, 2022
    Publication date: February 2, 2023
    Inventors: Kailash Vijayakumar, Remco Henricus Wilhelmus Pijnenburg, Willem Frederik Adrianus Besling, Sophie Guillemin, Jörg Siegert
  • Patent number: 11535512
    Abstract: The disclosure relates to a method for manufacturing a planarized etch-stop layer, ESL, for a hydrofluoric acid, HF, vapor phase etching process. The method includes providing a first planarized layer on top of a surface of a substrate, the first planarized layer having a patterned and structured metallic material and a filling material. The method further includes depositing on top of the first planarized layer the planarized ESL of an ESL material with low HF etch rate, wherein the planarized ESL has a low surface roughness and a thickness of less than 150 nm, in particular of less than 100 nm.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 27, 2022
    Assignee: AMS AG
    Inventors: Alessandro Faes, Sophie Guillemin, Joerg Siegert, Karl Tuttner
  • Patent number: 11492251
    Abstract: In an embodiment, a method for manufacturing a micro-electro-mechanical systems (MEMS) transducer device includes providing a substrate body with a surface, depositing an etch-stop layer (ESL) on the surface, depositing a sacrificial layer on the ESL, depositing a diaphragm layer on the sacrificial layer and removing the sacrificial layer, wherein depositing the sacrificial layer includes depositing a first sub-layer of a first material and depositing a second sub-layer of a second material, and wherein the first material and the second material are different materials.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 8, 2022
    Assignee: SCIOSENSE B.V.
    Inventors: Kailash Vijayakumar, Remco Henricus Wilhelmus Pijnenburg, Willem Frederik Adrianus Besling, Sophie Guillemin, Jörg Siegert
  • Publication number: 20220221363
    Abstract: In an embodiment a method for forming a pressure sensor device includes providing a pressure sensor on a substrate body, the pressure sensor comprising a membrane, depositing a top layer on top of the substrate body and the pressure sensor, connecting a cap body with the top layer, a mass of the cap body being approximately equal to a mass of the substrate body and introducing at least one opening in the cap body.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Inventors: Jörg Siegert, Willem Frederik Adrianus Besling, Coenraad Cornelis Tak, Martin Schrems, Franz Schrank
  • Patent number: 11313749
    Abstract: In an embodiment a pressure sensor device includes a substrate body, a pressure sensor having a membrane and a cap body having at least one opening, wherein the pressure sensor is arranged between the substrate body and the cap body in a vertical direction which is perpendicular to a main plane of extension of the substrate body, and wherein the mass of the substrate body amounts to at least 80% of the mass of the cap body and at most 120% of the mass of the cap body.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 26, 2022
    Assignee: SCIOSENSE B.V.
    Inventors: Joerg Siegert, Willem Frederik Adrianus Besling, Coenraad Cornelis Tak, Martin Schrems, Franz Schrank
  • Patent number: 11271134
    Abstract: A method for manufacturing an optical sensor is provided. The method comprises providing an optical sensor arrangement which comprises at least two optical sensor elements on a carrier, where the optical sensor arrangement comprises a light entrance surface at the side of the optical sensor elements facing away from the carrier. The method further comprises forming a trench between two optical sensor elements in a vertical direction which is perpendicular to the main plane of extension of the carrier, where the trench extends from the light entrance surface of the sensor arrangement at least to the carrier. Moreover, the method comprises coating the trench with an opaque material, forming electrical contacts for the at least two optical sensor elements on a back side of the carrier facing away from the optical sensor elements, and forming at least one optical sensor by dicing the optical sensor arrangement along the trench.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: March 8, 2022
    Assignee: AMS AG
    Inventors: Gregor Toschkoff, Thomas Bodner, Franz Schrank, Miklos Labodi, Joerg Siegert, Martin Schrems
  • Publication number: 20220059434
    Abstract: An intermetal dielectric and metal layers embedded in the intermetal dielectric are arranged on a substrate of semiconductor material. A via hole is formed in the substrate, and a metallization contacting a contact area of one of the metal layers is applied in the via hole. The metallization, the metal layer comprising the contact area and the intermetal dielectric are partially removed at the bottom of the via hole in order to form a hole penetrating the intermetal dielectric and extending the via hole. A continuous passivation is arranged on sidewalls within the via hole and the hole, and the metallization contacts the contact area around the hole. Thus the presence of a thin membrane of layers, which is usually formed at the bottom of a hollow through-substrate via, is avoided.
    Type: Application
    Filed: December 20, 2019
    Publication date: February 24, 2022
    Inventors: Bernhard LOEFFLER, Thomas BODNER, Joerg SIEGERT
  • Patent number: 11248976
    Abstract: Capacitive pressure sensors and other devices are disclosed. In an embodiment a semiconductor device includes a first electrode, a cavity over the first electrode and a second electrode including a suspended membrane over the cavity and electrically conductive anchor trenches laterally surrounding the cavity, wherein the anchor trenches include an inner anchor trench and an outer anchor trench, the outer anchor trench having rounded corners.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: February 15, 2022
    Assignee: SCIOSENSE B.V.
    Inventors: Willem Frederik Adrianus Besling, Casper Van Der Avoort, Remco Henricus Wilhelmus Pijnenburg, Olaf Wunnicke, Jörg Siegert, Alessandro Faes
  • Publication number: 20210387854
    Abstract: In an embodiment, a method for manufacturing a micro-electro-mechanical systems (MEMS) transducer device includes providing a substrate body with a surface, depositing an etch-stop layer (ESL) on the surface, depositing a sacrificial layer on the ESL, depositing a diaphragm layer on the sacrificial layer and removing the sacrificial layer, wherein depositing the sacrificial layer includes depositing a first sub-layer of a first material and depositing a second sub-layer of a second material, and wherein the first material and the second material are different materials.
    Type: Application
    Filed: November 4, 2019
    Publication date: December 16, 2021
    Inventors: Kailash Vijayakumar, Remco Henricus Wilhelmus Pijnenburg, Willem Frederik Adrianus Besling, Sophie Guillemin, Jörg Siegert
  • Publication number: 20210356342
    Abstract: In an embodiment a semiconductor transducer device includes a semiconductor body and a diaphragm having a first layer and a second layer, wherein a main extension plane of the diaphragm is arranged parallel to a surface of the semiconductor body, wherein the diaphragm is suspended at a distance from the semiconductor body in a direction perpendicular to the main extension plane of the diaphragm, wherein the second layer comprises titanium and/or titanium nitride, wherein the first layer comprises a material that is resistant to an etchant comprising fluorine or a fluorine compound, and wherein the second layer is arranged between the semiconductor body and the first layer.
    Type: Application
    Filed: October 16, 2019
    Publication date: November 18, 2021
    Inventors: Alessandro Faes, Jörg Siegert, Willem Frederik Adrianus Besling, Remco Henricus Wilhelmus Pijnenburg
  • Publication number: 20210359143
    Abstract: In an embodiment a method includes providing a semiconductor body, forming a sacrificial layer above a surface of the semiconductor body, applying a diaphragm on the sacrificial layer and removing the sacrificial layer by introducing an etchant into openings of the diaphragm, wherein applying the diaphragm comprises applying a first layer, reducing a roughness of a surface of the first layer facing away from the semiconductor body thereby providing a processed surface, and patterning and structuring the first layer to form the openings.
    Type: Application
    Filed: October 24, 2019
    Publication date: November 18, 2021
    Inventors: Alessandro Faes, Jörg Siegert, Willem Frederik Adrianus Besling, Remco Henricus Wilhelmus Pijnenburg
  • Patent number: 11107848
    Abstract: The semiconductor device for detection of radiation comprises a semiconductor substrate (1) with a main surface (11), a dielectric layer (6) comprising at least one compound of a semiconductor material, an integrated circuit (2) including at least one component sensitive to radiation (3), a wiring (4) of the integrated circuit embedded in an intermetal layer (8) of the dielectric layer (6), an electrically conductive through-substrate via (5) contacting the wiring, and an optical filter element (7) arranged immediately on the dielectric layer above the component sensitive to radiation. The dielectric layer comprises a passivation layer (9) at least above the through-substrate via, the passivation layer comprises a dielectric material that is different from the intermetal layer (8), and the wiring is arranged between the main surface and the passivation layer.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: August 31, 2021
    Assignee: AMS AG
    Inventors: Hubert Enichlmair, Franz Schrank, Joerg Siegert
  • Publication number: 20210214216
    Abstract: The disclosure relates to a method for manufacturing a planarized etch-stop layer, ESL, for a hydrofluoric acid, HF, vapor phase etching process. The method includes providing a first planarized layer on top of a surface of a substrate, the first planarized layer having a patterned and structured metallic material and a filling material. The method further includes comprises depositing on top of the first planarized layer the planarized ESL of an ESL material with low HF etch rate, wherein the planarized ESL has a low surface roughness and a thickness of less than 150 nm, in particular of less than 100 nm.
    Type: Application
    Filed: May 8, 2019
    Publication date: July 15, 2021
    Inventors: Alessandro FAES, Sophie GUILLEMIN, Joerg SIEGERT, Karl TUTTNER
  • Publication number: 20210020511
    Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.
    Type: Application
    Filed: April 3, 2019
    Publication date: January 21, 2021
    Inventors: Jochen Kraft, Georg Parteder, Stefan Jessenig, Franz Schrank, Jörg Siegert