Abstract: In an embodiment a method includes providing a semiconductor body, forming a sacrificial layer above a surface of the semiconductor body, applying a diaphragm on the sacrificial layer and removing the sacrificial layer by introducing an etchant into openings of the diaphragm, wherein applying the diaphragm comprises applying a first layer, reducing a roughness of a surface of the first layer facing away from the semiconductor body thereby providing a processed surface, and patterning and structuring the first layer to form the openings.

Abstract: In an embodiment a method for fabricating a photodetector device includes providing a carrier substrate, wherein a device layer is arranged at a main surface of the carrier substrate, and an insulating layer is arranged between the device layer and the carrier substrate, forming a plurality of photodetector elements in the device layer, forming an intermetal dielectric on the device layer, wherein contact pads electrically connected to the photodetector elements are embedded in the intermetal dielectric, forming pad openings in the intermetal dielectric, the pad openings reaching the contact pads so that the contact pads are accessible via the pad openings, mounting a handling substrate on the intermetal dielectric, removing the carrier substrate, singulating the plurality of photodetector elements such that a plurality of separate photodetector chips comprising one photodetector element are formed and releasing the photodetector chips from the handling substrate.

Abstract: A semiconductor device includes a substrate—with a rear surface and a main surface, an intermetal dielectric on the main surface of substrate, a metal layer embedded in the intermetal dielectric. The metal layer includes a top barrier layer. The top barrier layer is at a side of the metal layer facing away from the substrate. The semiconductor device also includes a through-substrate-via (TSV) reaching from the rear surface of the substrate to the top barrier layer of the metal layer. The TSV includes a metallization configured to electrically contact the metal layer from the rear surface of the substrate. The TSV includes a via hole. The via hole penetrates the substrate and the intermetal dielectric between the substrate and the metal layer. The via hole further penetrates the metal layer up to the top barrier layer.

Abstract: In an embodiment a semiconductor transducer device includes a semiconductor body and a diaphragm having a first layer and a second layer, wherein a main extension plane of the diaphragm is arranged parallel to a surface of the semiconductor body, wherein the diaphragm is suspended at a distance from the semiconductor body in a direction perpendicular to the main extension plane of the diaphragm, wherein the second layer comprises titanium and/or titanium nitride, wherein the first layer comprises a material that is resistant to an etchant comprising fluorine or a fluorine compound, and wherein the second layer is arranged between the semiconductor body and the first layer.

Abstract: In an embodiment, an integrated MEMS transducer device includes a substrate body having a first electrode on a substrate, an etch stop layer located on a surface of the substrate, a suspended micro-electro-mechanical systems (MEMS) diaphragm with a second electrode, an anchor structure with anchors connecting the MEMS diaphragm to the substrate body and a sacrificial layer in between the anchors of the anchor structure, the sacrificial layer including a first sub-layer of a first material, wherein the first sub-layer is arranged on the etch stop layer, a second sub-layer of a second material, wherein the second sub-layer is arranged on the first sub-layer, and wherein the first and the second material are different materials.

Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.

Abstract: A capacitive sensor is disclosed. In an embodiment a semiconductor device includes a die including a capacitive pressure sensor integrated on a CMOS circuit, wherein the capacitive pressure sensor includes a first electrode and a second electrode separated from one another by a cavity, the second electrode including a suspended tensile membrane, and wherein the first electrode is composed of one or more aluminum-free layers containing Ti.

Abstract: In an embodiment, an integrated MEMS transducer device includes a substrate body having a first electrode on a substrate, an etch stop layer located on a surface of the substrate, a suspended micro-electro-mechanical systems (MEMS) diaphragm with a second electrode, an anchor structure with anchors connecting the MEMS diaphragm to the substrate body and a sacrificial layer in between the anchors of the anchor structure, the sacrificial layer including a first sub-layer of a first material, wherein the first sub-layer is arranged on the etch stop layer, a second sub-layer of a second material, wherein the second sub-layer is arranged on the first sub-layer, and wherein the first and the second material are different materials.

Abstract: In an embodiment, a method for manufacturing a micro-electro-mechanical systems (MEMS) transducer device includes providing a substrate body with a surface, depositing an etch-stop layer (ESL) on the surface, depositing a sacrificial layer on the ESL, depositing a diaphragm layer on the sacrificial layer and removing the sacrificial layer, wherein depositing the sacrificial layer includes depositing a first sub-layer of a first material and depositing a second sub-layer of a second material, and wherein the first material and the second material are different materials.

Abstract: In an embodiment a method for forming a pressure sensor device includes providing a pressure sensor on a substrate body, the pressure sensor comprising a membrane, depositing a top layer on top of the substrate body and the pressure sensor, connecting a cap body with the top layer, a mass of the cap body being approximately equal to a mass of the substrate body and introducing at least one opening in the cap body.

Abstract: Capacitive pressure sensors and other devices are disclosed. In an embodiment a semiconductor device includes a first electrode, a cavity over the first electrode and a second electrode including a suspended membrane over the cavity and electrically conductive anchor trenches laterally surrounding the cavity, wherein the anchor trenches include an inner anchor trench and an outer anchor trench, the outer anchor trench having rounded corners.

Abstract: In an embodiment, a method for manufacturing a micro-electro-mechanical systems (MEMS) transducer device includes providing a substrate body with a surface, depositing an etch-stop layer (ESL) on the surface, depositing a sacrificial layer on the ESL, depositing a diaphragm layer on the sacrificial layer and removing the sacrificial layer, wherein depositing the sacrificial layer includes depositing a first sub-layer of a first material and depositing a second sub-layer of a second material, and wherein the first material and the second material are different materials.

Abstract: In an embodiment a semiconductor transducer device includes a semiconductor body and a diaphragm having a first layer and a second layer, wherein a main extension plane of the diaphragm is arranged parallel to a surface of the semiconductor body, wherein the diaphragm is suspended at a distance from the semiconductor body in a direction perpendicular to the main extension plane of the diaphragm, wherein the second layer comprises titanium and/or titanium nitride, wherein the first layer comprises a material that is resistant to an etchant comprising fluorine or a fluorine compound, and wherein the second layer is arranged between the semiconductor body and the first layer.

Abstract: In an embodiment a method includes providing a semiconductor body, forming a sacrificial layer above a surface of the semiconductor body, applying a diaphragm on the sacrificial layer and removing the sacrificial layer by introducing an etchant into openings of the diaphragm, wherein applying the diaphragm comprises applying a first layer, reducing a roughness of a surface of the first layer facing away from the semiconductor body thereby providing a processed surface, and patterning and structuring the first layer to form the openings.

Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.

Abstract: Capacitive pressure sensors and other devices are disclosed. In an embodiment a semiconductor device includes a first electrode, a cavity over the first electrode and a second electrode including a suspended membrane over the cavity and electrically conductive anchor trenches laterally surrounding the cavity, wherein the anchor trenches include an inner anchor trench and an outer anchor trench, the outer anchor trench having rounded corners.

Abstract: A capacitive sensor is disclosed. In an embodiment a semiconductor device includes a die including a capacitive pressure sensor integrated on a CMOS circuit, wherein the capacitive pressure sensor includes a first electrode and a second electrode separated from one another by a cavity, the second electrode including a suspended tensile membrane, and wherein the first electrode is composed of one or more aluminum-free layers containing Ti.

Abstract: A semiconductor substrate (1) is provided with a structure (3) on an upper side (2), and an additional substrate (4) provided for handling the semiconductor substrate is likewise structured on an upper side (5). The structuring of the additional substrate takes place in at least partial correspondence with the structure of the semiconductor substrate. The structured upper sides of the semiconductor substrate and the additional substrate are positioned such that they face one another and are permanently connected to one another. Subsequently, the semiconductor substrate is thinned from the rear side (6), and the additional substrate is removed at least to such a degree that the structure of the semiconductor substrate is exposed to the extent required for the further use.

Abstract: A semiconductor substrate (1) is provided with a structure (3) on an upper side (2), and an additional substrate (4) provided for handling the semiconductor substrate is likewise structured on an upper side (5). The structuring of the additional substrate takes place in at least partial correspondence with the structure of the semiconductor substrate. The structured upper sides of the semiconductor substrate and the additional substrate are positioned such that they face one another and are permanently connected to one another. Subsequently, the semiconductor substrate is thinned from the rear side (6), and the additional substrate is removed at least to such a degree that the structure of the semiconductor substrate is exposed to the extent required for the further use.

Abstract: Through the intermetal dielectric (2) and the semiconductor material of the substrate (1) a contact hole is formed, and a contact area of a connection metal plane (3) that faces the substrate is exposed in the contact hole. A metallization (11) is applied, which forms a connection contact (12) on the contact area, a through-contact (13) in the contact hole and a connection contact (20) on a contact area facing away from the substrate and/or on a vertical conductive connection (15) of the upper metal plane (24).