Abstract: A self-test circuit for an integrated circuit, having a plurality of scan chains is provided, wherein each of the scan chains has a plurality of first memory elements, a data input for providing the scan chain with test data, wherein the data input is connected to one of the first memory elements, a plurality of second memory elements, and a switching apparatus having a first and a second switching position, which switching apparatus is coupled between the first memory elements and the second memory elements and is configured to respectively connect a last one of the first memory elements to a data output in the first switching position and to respectively connect the last one of the first memory elements to a first one of the second memory elements in the second switching position.

Abstract: A self-test circuit for an integrated circuit, having a plurality of scan chains is provided, wherein each of the scan chains has a plurality of first memory elements, a data input for providing the scan chain with test data, wherein the data input is connected to one of the first memory elements, a plurality of second memory elements, and a switching apparatus having a first and a second switching position, which switching apparatus is coupled between the first memory elements and the second memory elements and is configured to respectively connect a last one of the first memory elements to a data output in the first switching position and to respectively connect the last one of the first memory elements to a first one of the second memory elements in the second switching position.

Abstract: A method and apparatus for testing by sampling vectors circuit modules designated as channel models or as control modules and containing scan chains. Use is made of a test register which provides at least one control sampling mode signal for control modules and furthermore provides at least one channel sampling mode signal for channel modules. Channel modules and control modules can occur as circuit modules multiply with identical scan chains, enabling efficient testing in a manner that saves memory space. A logic is designed for the read-out of sampling output signals after testing of the scan chains via a read-out terminal unit of a test device, thus providing a comparison with desired sampling output signals for channel modules or for control modules in a comparator unit.

Abstract: An integrated circuit is characterized in that circuit parts contained therein are connected to one another via an interface containing at least one scan register chain. The at least one scan register chain is configured such that data can be input into the scan register chain either via the output terminals of one of the circuit parts or via the input and/or output terminals of the integrated circuit. In addition, data can be output from the scan register chain either at the input terminals of one of the circuit parts or at the input and/or output terminals of the integrated circuit.

Abstract: A method and apparatus for testing by sampling vectors circuit modules designated as channel models or as control modules and containing scan chains. Use is made of a test register which provides at least one control sampling mode signal for control modules and furthermore provides at least one channel sampling mode signal for channel modules. Channel modules and control modules can occur as circuit modules multiply with identical scan chains, enabling efficient testing in a manner that saves memory space. A logic is designed for the read-out of sampling output signals after testing of the scan chains via a read-out terminal unit of a test device, thus providing a comparison with desired sampling output signals for channel modules or for control modules in a comparator unit.