Abstract: An electronic device is disclosed. The electronic device includes: a first doped region of a first doping type arranged in a first semiconductor layer of a second doping type complementary to the first doping type; an insulation layer formed on top of the first semiconductor layer and adjoining the first doped region; at least two active device regions arranged in a second semiconductor layer formed on top of the insulation layer; and an electrical connection between one of the at least two active device regions and the first doped region. Each of the at least two active device regions is arranged adjacent to the first doped region and separated from the first doped region by the insulation layer.

Abstract: A lateral high-voltage transistor includes a semiconductor substrate, a body region formed by dopant implantation in the semiconductor substrate, the body region having a lateral boundary, a dielectric layer arranged over the semiconductor substrate, and a structured gate layer arranged over the dielectric layer. The structured gate layer overlaps the body region in the semiconductor substrate in a zone between the lateral boundary of the body region and a gate edge of the structured gate layer. The lateral boundary of the body region is a boundary defined by dopant implantation.

Abstract: A lateral high-voltage transistor includes a semiconductor substrate, a body region formed by dopant implantation in the semiconductor substrate, the body region having a lateral boundary, a dielectric layer arranged over the semiconductor substrate, and a structured gate layer arranged over the dielectric layer. The structured gate layer overlaps the body region in the semiconductor substrate in a zone between the lateral boundary of the body region and a gate edge of the structured gate layer. The lateral boundary of the body region is a boundary defined by dopant implantation.

Abstract: A transistor device includes: a semiconductor substrate having a doping concentration of a first dopant type; a highly doped source region of a second dopant type formed in a first surface of the semiconductor substrate; a first highly doped drain region of the second dopant type formed in the first surface; a gate structure arranged on the first surface and including a gate electrode formed on the first surface; and a first lightly doped region formed in the first surface and extending from the highly doped source region under the gate electrode. A channel region extends between the first lightly doped region and the highly doped drain region. The channel region has an average doping level of the first dopant type of n×10x that varies by less than 0.5×n×10X between the first lightly doped region and the highly doped drain region along the lateral direction parallel to the first surface.

Abstract: A method of manufacturing a lateral transistor is described. The method includes providing a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate. A gate layer is formed over the dielectric layer. A photoresist layer is applied over the gate layer. The photoresist layer is opened by lithography to form a first opening of a first opening size in the photoresist layer. The first opening is transferred into a second opening of a second opening size, the second opening being either formed in the photoresist layer or in an auxiliary layer. A body region is formed in the semiconductor substrate by dopant implantation. Further the gate layer is structured to form a gate edge. An overlap between the structured gate layer and the body region is controlled by an offset between the first opening size and the second opening size.

Abstract: An electronic device is disclosed. The electronic device includes: a first doped region of a first doping type arranged in a first semiconductor layer of a second doping type complementary to the first doping type; an insulation layer formed on top of the first semiconductor layer and adjoining the first doped region; at least two active device regions arranged in a second semiconductor layer formed on top of the insulation layer; and an electrical connection between one of the at least two active device regions and the first doped region. Each of the at least two active device regions is arranged adjacent to the first doped region and separated from the first doped region by the insulation layer.

Abstract: A method of manufacturing a lateral transistor is described. The method includes providing a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate. A gate layer is formed over the dielectric layer. A photoresist layer is applied over the gate layer. The photoresist layer is opened by lithography to form a first opening of a first opening size in the photoresist layer. The first opening is transferred into a second opening of a second opening size, the second opening being either formed in the photoresist layer or in an auxiliary layer. A body region is formed in the semiconductor substrate by dopant implantation. Further the gate layer is structured to form a gate edge. An overlap between the structured gate layer and the body region is controlled by an offset between the first opening size and the second opening size.

Abstract: A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to pressure sensors and methods of manufacture. The structure includes: a top membrane of semiconductor material having edges defined by epitaxial material and a liner material; a back gate under the top membrane; and a cavity defined between the top membrane and the back gate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to pressure sensors and methods of manufacture. The structure includes: a top membrane of semiconductor material having edges defined by epitaxial material and a liner material; a back gate under the top membrane; and a cavity defined between the top membrane and the back gate.

Abstract: A semiconductor device includes an SOI substrate having a base substrate material, an active semiconductor layer positioned above the base substrate material and a buried insulating material layer positioned between the base substrate material and the active semiconductor layer. A gate structure is positioned above the active semiconductor layer and a back gate region is positioned in the base substrate material below the gate structure and below the buried insulating material layer. An isolation region electrically insulates the back gate region from the surrounding base substrate material, wherein the isolation region includes a plurality of implanted well regions that laterally contact and laterally enclose the back gate region and an implanted isolation layer that is formed below the back gate region.

Abstract: In fully depleted SOI transistors, specifically designed semiconductor materials may be provided for different types of transistors, thereby, for instance, enabling a reduction of hot carrier injection in transistors that are required to be operated at a moderately high operating voltage. To this end, well-controllable epitaxial growth techniques may be applied selectively for one type of transistor, while not unduly affecting the adjustment of material characteristics of a different type of transistor.

Abstract: A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating gates for a sub-set of the plurality of semiconductor fins and forming a first insulating layer between the plurality of semiconductor fins. The first insulating layer is recessed to a height less than the height of the plurality of semiconductor fins and sacrificial gates are formed over the sub-set of the plurality of semiconductor fins. A second insulating layer is formed between the sacrificial gates and, after that, the sacrificial gates are removed. Recesses are formed in the first insulating layer and sense gates and control gates are formed in the recesses for the sub-set of the plurality of semiconductor fins. The first and second insulating layers may be oxide layers.

Abstract: A method includes providing a semiconductor device structure including a substrate having a semiconductor-on-insulator (SOI) region and a hybrid region. A semiconductor device is provided in the SOI region. The semiconductor device includes a gate structure, a diode structure provided in the hybrid region and coupled to a substrate material of the SOI region, a supply circuit arrangement including first and second supply lines, a first resistor coupled between the first supply line and a first terminal of the diode structure, and a second resistor coupled between the second supply line and the substrate material positioned beneath the gate structure. At least one of the first and second resistors comprises a tunable resistor. A resistance of the tunable resistor is adjusted so as to adjust a threshold voltage (Vt) of the semiconductor device in dependence on an operating temperature of the SOI region.

Abstract: A semiconductor structure includes a support substrate including a semiconductor material, a buried insulation layer positioned above the support substrate, a semiconductor layer positioned above the buried insulation layer, the semiconductor layer having an upper surface and a lower surface, the lower surface being positioned on the buried insulation layer, and at least one nonvolatile memory cell. The nonvolatile memory cell includes a channel region, a front gate structure, a doped back gate region and a charge storage material. The channel region is located in the semiconductor layer. The front gate structure is located above the channel region and the upper surface of the semiconductor layer. The doped back gate region is located in the support substrate below the channel region. The charge storage material is embedded at least into a portion of the buried insulation layer between the channel region and the back gate region.

Abstract: In fully depleted SOI transistors, specifically designed semiconductor materials may be provided for different types of transistors, thereby, for instance, enabling a reduction of hot carrier injection in transistors that are required to be operated at a moderately high operating voltage. To this end, well-controllable epitaxial growth techniques may be applied selectively for one type of transistor, while not unduly affecting the adjustment of material characteristics of a different type of transistor.

Abstract: Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions.

Abstract: Capacitive structures in the device level of sophisticated MOS devices may be formed so as to exhibit a significantly reduced capacitance/voltage variability. To this end, a highly doped semiconductor region may be formed in the “channel” of the capacitive structure. For example, for a specified concentration of the dopant species and a specified range of the vertical dimension of the highly doped semiconductor region, a reduced variability of approximately 3% or less may be obtained for a voltage range of, for example, ±5 V.

Abstract: A method includes providing a semiconductor device structure including a substrate having a semiconductor-on-insulator (SOI) region and a hybrid region. A semiconductor device is provided in the SOI region. The semiconductor device includes a gate structure, a diode structure provided in the hybrid region and coupled to a substrate material of the SOI region, a supply circuit arrangement including first and second supply lines, a first resistor coupled between the first supply line and a first terminal of the diode structure, and a second resistor coupled between the second supply line and the substrate material positioned beneath the gate structure. At least one of the first and second resistors comprises a tunable resistor. A resistance of the tunable resistor is adjusted so as to adjust a threshold voltage (Vt) of the semiconductor device in dependence on an operating temperature of the SOI region.

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.