Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Abstract: An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.

Abstract: A photodiode comprises a semiconductor material having a p-n junction, the p-n junction being located between a first doping region of a first doping type and a second doping region of a second doping type, the second doping region comprising a highly doped layer and a lightly doped layer. A photodiode further comprises a voltage source being capable to apply a variable voltage between the first doping region and the lightly doped layer of the second doping region in order to vary the expansion of a space charge zone of the p-n junction.

Abstract: An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.

Abstract: Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. Further, the step of forming source and drain depressions at the gate stack in the semiconductor substrate includes that first depressions are formed for realizing channel connection regions in the semiconductor substrate, spacers are formed at the gate stack, and second depressions are formed using the spacers as a mask in the first depressions and in the semiconductor substrate.

Abstract: A method for fabricating an interconnect arrangement with increased capacitive coupling is described. A trench structure is formed in a first dielectric having a capacitor region with a first aspect ratio and an interconnect region with a second aspect ratio connected thereto. The trench structure of the interconnect region is completely filled by a first interconnect. The trench structure of the capacitor region is only partially filled by a first capacitor electrode and is completely filled by a capacitor dielectric and a second capacitor electrode. In a second dielectric formed thereon, a second interconnect with a contact via is formed, which is connected to the second capacitor electrode.

Abstract: An explanation is given of, inter alia, a circuit arrangement in which an intermediate layer (160) made of a dielectric material is arranged between two metal layers (102 and 104). The intermediate layer (160) is designed in such a way that the capacitance per unit area between the connection layers (102, 104) is greater than 0.5 fF/?m2.

Abstract: An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.

Abstract: Methods of fabricating an integrated circuit, in particular a dynamic random access memory are described. After forming memory cells on a semiconductor substrate a mirror layer is provided, said mirror layer covering the memory cells. Then logic devices are formed adjoining to said memory cells covered by said mirror layer, said forming of said logic devices including activating the dopants in dopant regions by means of a radiation annealing, said radiation being reflected by said mirror layer. After at least partly removing the mirror layer; a wiring of the memory cells and of the logic devices is formed.

Abstract: Process for forming a dielectric. The process may include forming the dielectric on a metallization and capacitor arrangement. The process allows the direct application of a dielectric layer to a copper-containing metallization. Accordingly, two process gases may be excited with different plasma powers per unit substrate area, or one process gas may be excited with a plasma and another process gas may not be excited.

Abstract: An integrated circuit includes a memory cell with a transistor. The transistor includes first and second doped portions, and a third portion disposed between the first and second doped portions. The first and the second doped portions and the third portion are disposed in a semiconductor substrate. The transistor further includes a gate electrode adjacent to the third portion, the gate electrode being insulated from the third portion. The gate electrode does not overlap at least one of the first and second doped portions, and a line connecting the first and the second portions extends substantially perpendicular to a surface of the substrate.

Abstract: An integrated layer stack arrangement, an optical sensor and a method for producing an integrated layer stack arrangement is disclosed. Generally, an integrated layer stack arrangement includes a plurality of layer stacks arranged on top of each other, each layer stack including a metal layer and a dielectric layer arranged; at least one photodiode integrated into the plurality of layer stacks; a trench arranged above the last least one photodiode, the trench extending through at least a portion of the plurality of layer stacks so that light impinging on the plurality of layer stacks impinges on the integrated photodiode along the trench; a first passivation partial layer applied on the plurality of layer stacks; and a second passivation partial layer applied on the plurality of layer stacks and a bottom and walls of the trench.

Abstract: A field-effect transistor (FET) with local source-drain insulation is described. The FET includes a semiconductor substrate, source and drain depressions, a depression insulation layer, an electrically conductive filling layer, a gate dielectric, and a gate layer. The depression insulation layer is formed at least in bottom regions of the source and drain depressions. The electrically conductive filling layer realizes source and drain regions and fills the source and drain depressions at a surface of the depression insulation layer. The gate dielectric is formed at a substrate surface between the source and drain depressions. The gate layer (is formed at a surface of the gate dielectric. The source and drain depressions have, in an upper region, a widening with a predetermined death for realizing defined channel connection regions.

Abstract: An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.

Abstract: Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.

Abstract: An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate.

Abstract: Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.