Abstract: The invention relates to a device for detecting an electric arc in an electronic assembly, having: a transmission unit for generating an output signal, and an evaluation unit for receiving the output signal, where the transmission unit and the evaluation unit are connected to one another, where the transmission unit comprises an oscillator unit that generates an output signal having a frequency and/or an amplitude, and where the evaluation unit is configured to detect deviations, caused by an arc, in the output signal from the transmission unit. There is in particular a provision to implement the oscillator unit by way of a modified Pierce oscillator having an inverter, where the quartz is replaced by a detector coil. The invention furthermore relates to an electronic assembly of a motor vehicle having an apparatus to be controlled, in particular having a heating apparatus and having said device, and to a method for detecting an electric arc in an electronic assembly.

Abstract: The invention relates to a device for detecting an electric arc in an electronic assembly, having: a transmission unit for generating an output signal, and an evaluation unit for receiving the output signal, where the transmission unit and the evaluation unit are connected to one another, where the transmission unit comprises an oscillator unit that generates an output signal having a frequency and/or an amplitude, and where the evaluation unit is configured to detect deviations, caused by an arc, in the output signal from the transmission unit. There is in particular a provision to implement the oscillator unit by way of a modified Pierce oscillator having an inverter, where the quartz is replaced by a detector coil. The invention furthermore relates to an electronic assembly of a motor vehicle having an apparatus to be controlled, in particular having a heating apparatus and having said device, and to a method for detecting an electric arc in an electronic assembly.

Abstract: A method for the PWM actuation of more than one HV component for converting the power required by the HV components, in which each HV component is actuated by means of an individual PWM control circuit, and to a device for carrying out the method, wherein individual PWM control circuits are provided for the PWM actuation of 2 . . . n HV components, and wherein means are provided for asymmetrically splitting the phase shifts of the individual PWM actuation provided by the PWM circuitry.

Abstract: A method for the PWM actuation of more than one HV component for converting the power required by the HV components, in which each HV component is actuated by means of an individual PWM control circuit, and to a device for carrying out the method, wherein individual PWM control circuits are provided for the PWM actuation of 2 . . . n HV components, and wherein means are provided for asymmetrically splitting the phase shifts of the individual PWM actuation provided by the PWM circuitry.

Abstract: An electronic memory arrangement having at least three memory areas, a memory control unit, and a writing memory-accessing unit configured to carry out write access. A reading memory-accessing unit is configured to carry out read accesses. The memory control unit determines read and write access to the at least three memory areas, and the memory control unit is configured such that after the writing of a first data packet to one of the three memory areas, a following second data packet to be written is written to one on the three memory area to which read access does not place simultaneously during the write access of the second data packet.

Abstract: An electronic communication system including at least first and a second communication units (master, slave) which are connected to one another by means of at least one first data line, wherein the communication system has a data transmission protocol which is designed such that at least one defined communication process comprises the transmission of a synchronization packet (frame sync) and/or of an identification packet (ID) and/or a command packet (CMD) and/or of an address packet (ADDR) from the first communication unit (master) to at least the second communication unit (slave) via at least the first data line.

Abstract: A communication system having at least one first and a second communication unit. The first communication unit has a counter memory unit which stores a counter value, and is designed such that the occurrence of a first communication event prompts the counter value in the counter memory unit to be changed in a defined first manner. At least the occurrence of a defined reference event is followed by the counter value in the counter memory unit being changed in a defined second manner. In the course of a second defined communication event, the first communication unit transmits the current counter value in the counter memory unit to the second communication unit.

Abstract: An electronic communication unit which is in the form of a sensor and/or actuator unit, including at least a first status information processing module having a status memory unit which stores status information for the communication unit in the form of a status data item (stat), wherein the first status information processing module further includes a masking memory unit connected to the status memory unit and also a status processing element connected to the masking memory unit, wherein the first status information processing module is designed such that at least one status information item from the status data item (stat) is selected by the masking memory unit and the resultant selective status data item (sel-stat) is processed by the status processing element such that the output of the latter provides a short status data item (k-stat) which has a shorter data word length than the selective status data item (sel-stat).

Abstract: An electronic communication unit which is in the form of a sensor and/or actuator unit, including at least a first status information processing module having a status memory unit which stores status information for the communication unit in the form of a status data item (stat), wherein the first status information processing module further includes a masking memory unit connected to the status memory unit and also a status processing element connected to the masking memory unit, wherein the first status information processing module is designed such that at least one status information item from the status data item (stat) is selected by the masking memory unit and the resultant selective status data item (sel-stat) is processed by the status processing element such that the output of the latter provides a short status data item (k-stat) which has a shorter data word length than the selective status data item (sel-stat).

Abstract: Disclosed herein is a communication system having at least one first and a second communication unit, wherein the first communication unit has a counter memory unit which stores a counter value (MSG_CNT), wherein the first communication unit is designed such that at least the occurrence of a first defined communication event prompts the counter value in the counter memory unit to be changed in at least one defined first manner, wherein at least the occurrence of a defined reference event is followed by the counter value in the counter memory unit being changed in at least one defined second manner, wherein at least in the course of a second defined communication event the first communication unit transmits the current counter value in the counter memory unit directly or indirectly to the second communication unit.

Abstract: An electronic communication system including at least first and a second communication units (master, slave) which are connected to one another by means of at least one first data line, wherein the communication system has a data transmission protocol which is designed such that at least one defined communication process comprises the transmission of a synchronization packet (frame sync) and/or of an identification packet (ID) and/or a command packet (CMD) and/or of an address packet (ADDR) from the first communication unit (master) to at least the second communication unit (slave) via at least the first data line.

Abstract: An electric connector with a tolerance compensator, includes a plug-in part and a counter part. An electric connection is established when the plug-in part including at least one electrically conductive pin is plugged into the counter part in the z-direction of a Cartesian coordinate system. The counter part has volume elastic properties, is electrically conductive and forms a predetermined volume. The counter part is limited in the z-direction by, respectively, one contact surface. In order to establish an electric connection, the at least one electrically conductive pin is aligned essentially in the counterpart in the z-direction and traverses a contact surface in an essentially perpendicular manner. The volume area of the counter part is calculated such that the pin reaches the volume allowing a reliable electric connected to be established, in the framework of a permitted path tolerance in the x- and/or y-direction when plugging together.