Patents by Inventor Jürgen Zacherl

Jürgen Zacherl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10842030
    Abstract: A method of through-plating a circuit board having conductors formed on two sides. At least two holes are filled under compression pressure with a sintering paste. Subsequently, the sintering paste is dried and fired to form a cohesive bond with the ceramic substrate and fill the holes. Simultaneous filling of multiple holes having different hole diameters is accomplished using a printing screen with screen holes of different diameters. A single print parameter set is used. The printing screen here has at least one screen hole for filling a hole larger than the reference hole. The screen hole has an area-reducing and area-dividing geometry that divides the screen hole into at least two hole sections.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: November 17, 2020
    Assignee: VITESCO TECHNOLOGIES GMBH
    Inventors: Jürgen Zacherl, Erich Mattmann, Waldemar Brinkis
  • Publication number: 20200187366
    Abstract: A printing screen for use through-plating a printed circuit board. The printing screen has at least one screen hole for filling a larger hole compared to a reference hole in a ceramic substrate. This printing screen has an area-reducing and area-dividing geometry that divides the screen hole into at least two hole sections.
    Type: Application
    Filed: July 6, 2018
    Publication date: June 11, 2020
    Inventors: Jürgen Zacherl, Erich Mattmann, Waldemar Brinkis
  • Publication number: 20200187353
    Abstract: A printed circuit board, preferably for use in a fuel fill-level sensor and in a fuel fill-level measuring system, having conductor tracks formed on two sides of a ceramic substrate. The ceramic substrate has at least one metalized hole for through-contacting that connects the conductor tracks to one another. The hole of the sintered ceramic substrate is filled with a metal-containing sintering paste, which is introduced under pressure. In the fully sintered state, the paste enters into at least one integral bond with the ceramic substrate and completely fills the hole in so doing.
    Type: Application
    Filed: July 4, 2017
    Publication date: June 11, 2020
    Inventors: Erich MATTMANN, Waldemar BRINKIS, Jürgen ZACHERL
  • Publication number: 20200170123
    Abstract: A method of through-plating a circuit board having conductors formed on two sides. At least two holes are filled under compression pressure with a sintering paste. Subsequently, the sintering paste is dried and fired to form a cohesive bond with the ceramic substrate and fill the holes. Simultaneous filling of multiple holes having different hole diameters is accomplished using a printing screen with screen holes of different diameters. A single print parameter set is used. The printing screen here has at least one screen hole for filling a hole larger than the reference hole. The screen hole has an area-reducing and area-dividing geometry that divides the screen hole into at least two hole sections.
    Type: Application
    Filed: July 6, 2018
    Publication date: May 28, 2020
    Inventors: Jürgen Zacherl, Erich Mattmann, Waldemar Brinkis
  • Patent number: 7782218
    Abstract: A device and a method for detecting seat occupancy, with the device including first and second sensor elements associated with a respective seat surface. First and second weight-dependent sensor signals are electrically obtainable from the sensor elements. The seat occupancy is determined by taking either the first or the second sensor signals in dependence on an ambient temperature.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: August 24, 2010
    Assignee: Continental Automotive GmbH
    Inventors: Michael Krempl, Gerhard Wild, Jürgen Zacherl
  • Patent number: 7384822
    Abstract: The invention relates to a packaging for semiconductor components such as FBGA packages in BOC technology or the like, wherein at least the back and the lateral edges of a chip (2) mounted on a substrate are enclosed by a mold coating (6), the casting compound used for the mold coating (6) being linked with the substrate and forming an integrated whole therewith. The invention further relates to a method for producing such a packaging for semiconductor components. The aim of the invention is to provide a packaging for semiconductor components which is characterized by reduced thermomechanical stress and at the same time a substantially improved adhesion of the mold coating to the substrate, thereby allowing for a higher package load.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: June 10, 2008
    Assignee: Infineon Technologies AG
    Inventors: Juergen Zacherl, Stephan Blaszczak, Martin Reiss, Sylke Ludewig
  • Patent number: 7229857
    Abstract: The invention relates to a method for producing a protection for the chip edges of electronic components that are not provided with a housing, according to which semiconductor chips provided with a laterally open bonding channel are mounted on a substrate with a tape interposed between. The invention further relates to a system for protecting chip edges.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: June 12, 2007
    Assignee: Infineon Technologies AG
    Inventors: Juergen Zacherl, Martin Reiss, Stephan Blaszczak
  • Publication number: 20060138632
    Abstract: The invention relates to a packaging for semiconductor components such as FBGA packages in BOC technology or the like, wherein at least the back and the lateral edges of a chip (2) mounted on a substrate are enclosed by a mold coating (6), the casting compound used for the mold coating (6) being linked with the substrate and forming an integrated whole therewith. The invention further relates to a method for producing such a packaging for semiconductor components. The aim of the invention is to provide a packaging for semiconductor components which is characterized by reduced thermomechanical stress and at the same time a substantially improved adhesion of the mold coating to the substrate, thereby allowing for a higher package load.
    Type: Application
    Filed: June 10, 2003
    Publication date: June 29, 2006
    Inventors: Juergen Zacherl, Stephan Blaszczak, Martin Reiss, Sylke Ludewig
  • Patent number: 6933595
    Abstract: The invention relates to an electronic device and a leadframe and to methods for producing the electronic device and the leadframe. The electronic device has a semiconductor chip with a top side fixed on a rewiring plate by a double-sided adhesive film. The underside of the rewiring plate has an edge region with through openings. The through openings are filled with a plastics compound that holds together the semiconductor chip and the rewiring plate by acting as a mechanical clip.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: August 23, 2005
    Assignee: Infineon Technologies AG
    Inventors: Martin Reiss, Jürgen Zacherl
  • Publication number: 20050064630
    Abstract: The invention relates to a method for producing a protection for the chip edges of electronic components that are not provided with a housing, according to which semiconductor chips provided with a laterally open bonding channel are mounted on a substrate with a tape interposed between. The invention further relates to a system for protecting chip edges.
    Type: Application
    Filed: July 14, 2004
    Publication date: March 24, 2005
    Inventors: Juergen Zacherl, Martin Reiss, Stephan Blaszscak