Abstract: A system and method for testing a memory device is disclosed. One embodiment includes a plurality of memory cells. Each of the memory cells can be controlled by an address. A test memory for storing test results is provided. An address comparing unit is configured to determine whether the address of a memory cell lies in a predetermined address space. A controllable unit for storing test results is connected with the test memory and the address comparing unit. The controllable unit is controlled by the address comparing unit such that error information of the tested memory cell is only stored in the test memory if the address of the tested memory cell lies in the selected address space.

Abstract: A data signal is detected and compared with a reference value. A displacement time is determined as a function of the difference between the reference value and the signal level of the data signal. The data signal is buffer-stored and output in a manner that is temporally delayed by the displacement time. Accordingly, the data signal has a predetermined value at a predetermined point in time after the buffer-storage. Consequently, the data signal waveform can be defined with respect to time. As a result, a precise signal waveform is prescribed, and time periods for detecting the data signal can be precisely defined.

Abstract: A method for synchronizing a data exchange between a data source and a control device is provided. A synchronization request signal is first transmitted via the bus system to the data source, which then measures a signal propagation time from the control device to the data source. In the data source, a transmission delay time is set which is dependent on the measured signal propagation time. Data which are to be transmitted are delayed by the transmission delay time. A bus system for synchronizing a data exchange is also provided. After receiving a synchronization request signal, the data source measures signal propagation times and sets a transmission delay time in a transmission delay device on the basis of the measured signal propagation times.

Abstract: A memory cell has a transistor, a capacitor, and a second transistor that is formed as a parasitic field-effect transistor. The parasitic field-effect transistor is provided in order to produce an electrically conductive connection between a voltage source and the inner electrode of the capacitor. Stabilization of a charge state of the capacitor is automatically achieved in this way.