Abstract: An embodiment is directed to a hardware circuit for encrypting and/or decrypting data transmitted between a processor and a memory. The circuit is situated between the processor and memory. The circuit includes a first interface communicatively coupled to the processor via a set of buses. The circuit also includes a second interface communicatively coupled to the memory. The circuit further includes hardware logic capable of executing an encryption operation on data transmitted between the processor and memory, without adding latency to data transmission speed between the processor and the memory. The hardware logic is configured to encrypt data received at the first interface from the processor, and transmit the encrypted data to the memory via the second interface. The hardware logic is also configured to decrypt data received at the second interface from the memory, and transmit the decrypted data to the processor via the first interface.

Abstract: An embodiment is directed to a hardware circuit for performing operations on data transmitted between a processor and memory. The hardware circuit includes a first interface communicatively coupled to the processor. The first interface configured to emulate a first protocol of the memory. The hardware circuit further includes a second interface communicatively coupled to the memory. The second interface configured to emulates a second protocol of the processor. The hardware circuit also includes hardware logic configured with a bi-directional path, such that each of the first and second interfaces is associated with a different direction of the bi-directional path. The bi-directional path is configured to execute an operation on data received at both the first interface and the second interface.