Patents by Inventor J. Scott Elder

J. Scott Elder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100134040
    Abstract: A power source provides an output voltage to drive a plurality of light emitting diode (LED) strings. A feedback controller monitors the tail voltages of the LED strings to identify the minimum tail voltage and adjusts the output voltage based on a relationship between the minimum tail voltage and a reference voltage. The feedback controller implements precharging of the output voltage, including one or both of short-term precharging or long-term precharging. Further, the feedback controller incorporates a track/hold circuit that tracks the minimum tail voltage while the LED strings are active and holds the minimum tail voltage at the last tracked minimum tail voltage while the LED strings are inactive and uses the held minimum tail voltage for controlling the output voltage while the LED strings are inactive so as to permit the power source to supply an appropriate output voltage when the LED strings are subsequently activated again.
    Type: Application
    Filed: December 3, 2008
    Publication date: June 3, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: J. Scott Elder
  • Patent number: 7358809
    Abstract: The performance of precision analog integrated electronic circuits is directly related to the degree of matching between electrical circuit elements. Any residual mismatch of circuit elements after manufacturing must be calibrated out using numerous techniques such as adjusting potentiometers, trimming capacitors, modifying binary-weighted resistor strings, etc. Prior art matching techniques entail the use of large area circuit elements or a large number of elements arranged in a prescribed manner on the surface of a silicon die to minimize the residual calibration. The present invention utilizes a multiplicity of circuit elements that are interconnected in distinct groups to achieve a higher degree of element matching and the ensuing benefits thereof. The elements are interconnected to yield a prescribed minimum mismatch error.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: April 15, 2008
    Inventor: J. Scott Elder