Abstract: A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

Abstract: A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

Abstract: By modeling real-world application objects with complex structures, behaviors, and operations described by a schema which is enforced by the hardware/software interface system, various embodiments of the present invention provide rich sub-typing functionality by extending Items (and Item types) using “Extensions” which provide additional data structures (Properties, Relationships, etc.) to already existing Items type structures. Extensions are strongly typed instances that cannot exist independently and must be attached to an Item or a Nested Element. Extensions are also intended to address “multi-typing” issues by enabling the overlap of type instances (e.g., a Document may be a “legal document” as well a “secure document”).

Abstract: By modeling real-world application objects with complex structures, behaviors, and operations described by a schema which is enforced by the hardware/software interface system, various embodiments of the present invention provide rich sub-typing functionality by extending Items (and Item types) using “Extensions” which provide additional data structures (Properties, Relationships, etc.) to already existing Items type structures. Extensions are strongly typed instances that cannot exist independently and must be attached to an Item or a Nested Element. Extensions are also intended to address “multi-typing” issues by enabling the overlap of type instances (e.g., a Document may be a “legal document” as well a “secure document”).

Abstract: A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.

Abstract: Message publish/subscribe systems are required to process high message volumes with reduced latency and performance bottlenecks. The hardware-based messaging appliance proposed by the present invention is designed for high-volume, low-latency messaging. The hardware-based messaging appliance is part of a publish/subscribe middleware system. With the hardware-based messaging appliances, this system operates to, among other things, reduce intermediary hops with neighbor-based routing, introduce efficient native-to-external and external-to-native protocol conversions, monitor system performance, including latency, in real time, employ topic-based and channel-based message communications, and dynamically optimize system interconnect configurations and message transmission protocols.

Abstract: Message publish/subscribe systems are required to process high message volumes with reduced latency and performance bottlenecks. The intelligent messaging application programming interface (API) introduced by the present invention is designed for high-volume, low-latency messaging. The API is part of a publish/subscribe middleware system. With the API, this system operates to, among other things, monitor system performance, including latency, in real time, employ topic-based and channel-based message communications, and dynamically optimize system interconnect configurations and message transmission protocols.

Abstract: Message publish/subscribe systems are required to process high message volumes with reduced latency and performance bottlenecks. The end-to-end middleware architecture proposed by the present invention is designed for high-volume, low-latency messaging by, among other things, reducing intermediary hops with neighbor-based routing, introducing efficient native-to-external and external-to-native protocol conversions, monitoring system performance, including latency, in real time, employing topic-based and channel-based message communications, and dynamically optimizing system interconnect configurations and message transmission protocols.

Abstract: Message publish/subscribe systems are required to process high message volumes with reduced latency and performance bottlenecks. The end-to-end middleware architecture proposed by the present invention is designed for high-volume, low-latency messaging and with guaranteed delivery quality of service through data caching that uses a caching engine (CE) with storage and storage services. In a messaging, a messaging appliance (MA) receives and routes messages, but it first records all or a subset of the routed messages by sending a copy to the CE. Then, for a predetermined period of time, recorded messages are available for retransmission upon request by any component in the messaging system, thereby providing guaranteed-connected and guaranteed-disconnected delivery quality of service as well as partial data publication service.

Abstract: Message publish/subscribe systems are required to process high message volumes with reduced latency and performance bottlenecks. The end-to-end middleware architecture proposed by the present invention is designed for high volume, low-latency messaging by providing, among other things, a central, single point provisioning and management for configuration, provisioning and monitoring system performance. This functionality complements the reduction of intermediary hops through neighbour-based routing and dynamic, real time, optimizing of system interconnect configurations and message transmission protocols.

Abstract: A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

Abstract: A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.

Abstract: A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

Abstract: Various embodiments of the present invention are directed to a computer system comprising a plurality of Items, Item Folders, and a hardware/software interface system. The Items constitute discrete storable units of information that can be manipulated by a hardware/software interface system. The Item Folders, which are Items themselves, constitute an organizational structure for Items. Each Item belongs to at least one Item Folder, and Items may belong to more than one Item Folder. However, an Item is not necessarily owned by any particular Item Folder, such that the deletion of said Item Folder does not automatically result in the deletion of said Item. Instead, an Item might be automatically deleted only when it no longer belongs to any Item Folder or, alternately, and Item may be automatically deleted when it is a member of only one Item Folder and that Item Folder is deleted.

Abstract: Various embodiments of the present invention are directed to a hardware/software interface system for a computer system for manipulating a plurality of discrete units of information at a hardware/software interface system level (“Items”), said Items interconnected by Relationships and where Items have Relationships to other Items. One such relationship between Items may be for the purposes of logically denoting to the hardware/software interface system wether one Item is public and accessible or private and unaccessible to another Item.

Abstract: Various embodiments of the present invention are directed to a method for manipulating a plurality of discrete units of information (“Items”) in a hardware/software interface system for a computer system, said method comprising interconnecting said Items with a plurality of Relationships and managing said Relationships at the hardware/software interface system level. Each Relationship constitutes, at the hardware/software interface system level, a mapping between a pair of Items that said Relationship interconnects. Moreover, each Relationship may have properties of its own distinct and separate from the properties of the Items it interconnects.

Abstract: By modeling real-world application objects with complex structures, behaviors, and operations described by a schema which is enforced by the hardware/software interface system, various embodiments of the present invention provide rich sub-typing functionality by extending Items (and Item types) using “Extensions” which provide additional data structures (Properties, Relationships, etc.) to already existing Items type structures. Extensions are strongly typed instances that cannot exist independently and must be attached to an Item or a Nested Element. Extensions are also intended to address “multi-typing” issues by enabling the overlap of type instances (e.g., a Document may be a “legal document” as well a “secure document”).

Abstract: Various embodiments of the present invention are directed to a data store comprising Items, Elements, and Relationships. An Item is a unit of data storable in a data store and further comprises said Element and said Relationship. An Element is an instance of a type comprising one or more fields. A Relationship is a link between at least two Items. The data store further comprising a Core Schema to define a set of Core Items by which a hardware/software interface system understands and directly processes said set of Core Items in a predetermined and predictable way. The Core Items are derived (directly or indirectly) from a common single Base Item which, in turn, is a foundational Item in a Base Schema.

Abstract: Various embodiments of the present invention are directed to a method, in a computer system, for a hardware/software interface system to manipulate a plurality of discrete units of information having properties understandable by said hardware/software interface system (“Items”), said method comprising the use of a core schema to define a set of core Items which said hardware/software interface system understands and can directly process in a predetermined and predictable way. The core Items are derived from the base Item type. In certain embodiments, the Items types in the core schema cannot be directly subtyped but may instead be extended to incorporate additional properties in specific contexts without becoming inconsistent in other contexts that only comprehend the core Item type.

Abstract: Various embodiments of the present invention are directed to a method, in a computer system, for a hardware/software interface system to manipulate a plurality of discrete units of information having properties understandable by said hardware/software interface system (“Items”). The method uses a base schema comprising at least one of an Item as a base Item from which all other Items are derived, and at least one of a property as a base property from which all other properties are derived. Furthermore, an Item may comprise a property for referencing Categories to which the Item is a member. The Item may also comprises a property for a unique identification of that Item in the hardware/software interface system.